Datasheet

 2003-2013 Microchip Technology Inc. DS39609C-page 337
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 26-24: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 26-23: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 26-25: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 26-24: USART SYNCHRONOUS RECEIVE REQUIREMENTS
121
121
120
122
RC6/TX1/CK1
RC7/RX1/DT1
pin
pin
Note: Refer to Figure 26-6 for load conditions.
Param
No.
Symbol Characteristic Min Max Units Conditions
120 T
CKH2DTV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid PIC18FXX20 — 40 ns
PIC18LFXX20 — 100 ns VDD = 2.0V
121 T
CKRF Clock Out Rise Time and Fall Time
(Master mode)
PIC18FXX20 — 20 ns
PIC18LFXX20 — 50 ns VDD = 2.0V
122 TDTRF Data Out Rise Time and Fall Time PIC18FXX20 — 20 ns
PIC18LFXX20 — 50 ns V
DD = 2.0V
125
126
RC6/TX1/CK1
RC7/RX1/DT1
pin
pin
Note: Refer to Figure 26-6 for load conditions.
Param
No.
Symbol Characteristic Min Max Units Conditions
125 T
DTV2CKL SYNC RCV (MASTER & SLAVE)
Data Hold before CK  (DT hold time) 10 — ns
126 T
CKL2DTL Data Hold after CK  (DT hold time) 15 — ns