Datasheet

PIC18F6520/8520/6620/8620/6720/8720
DS39609C-page 330  2003-2013 Microchip Technology Inc.
TABLE 26-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
FIGURE 26-18: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
Param
No.
Symbol Characteristic Min Max Units Conditions
71 TSCH SCK Input High Time
(Slave mode)
Continuous 1.25 TCY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 T
SCL SCK Input Low Time
(Slave mode)
Continuous 1.25 TCY + 30 — ns
72A Single Byte 40 — ns (Note 1)
73 T
DIV2SCH,
T
DIV2SCL
Setup Time of SDI Data Input to SCK Edge 100 — ns
73A TB2B Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)
74 T
SCH2DIL,
T
SCL2DIL
Hold Time of SDI Data Input to SCK Edge 100 — ns
75 TDOR SDO Data Output Rise Time PIC18FXX20 — 25 ns
PIC18LFXX20 — 45 ns V
DD = 2.0V
76 TDOF SDO Data Output Fall Time — 25 ns
78 TSCR SCK Output Rise Time
(Master mode)
PIC18FXX20 — 25 ns
PIC18LFXX20 — 45 ns V
DD = 2.0V
79 TSCF SCK Output Fall Time (Master mode) — 25 ns
80 TSCH2DOV,
T
SCL2DOV
SDO Data Output Valid after SCK
Edge
PIC18FXX20 — 50 ns
PIC18LFXX20 — 100 ns V
DD = 2.0V
81 TDOV2SCH,
T
DOV2SCL
SDO Data Output Setup to SCK Edge T
CY —ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73
74
75, 76
77
78
79
80
79
78
SDI
MSb
LSb
bit 6 - - - - - -1
MSb In bit 6 - - - -1 LSb In
83
Note: Refer to Figure 26-6 for load conditions.