Datasheet

 2003-2013 Microchip Technology Inc. DS39609C-page 329
PIC18F6520/8520/6620/8620/6720/8720
TABLE 26-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
FIGURE 26-17: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
Param
No.
Symbol Characteristic Min Max Units Conditions
70 T
SSL2SCH,
T
SSL2SCL
SS
 to SCK  or SCK  Input TCY —ns
71 T
SCH SCK Input High Time
(Slave mode)
Continuous 1.25 TCY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 T
SCL SCK Input Low Time
(Slave mode)
Continuous 1.25 TCY + 30 — ns
72A Single Byte 40 — ns (Note 1)
73 T
DIV2SCH,
T
DIV2SCL
Setup Time of SDI Data Input to SCK Edge 100 — ns
73A TB2B Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)
74 T
SCH2DIL,
T
SCL2DIL
Hold Time of SDI Data Input to SCK Edge 100 — ns
75 TDOR SDO Data Output Rise Time PIC18FXX20 — 25 ns
PIC18LFXX20 — 45 ns V
DD = 2.0V
76 TDOF SDO Data Output Fall Time — 25 ns
78 TSCR SCK Output Rise Time
(Master mode)
PIC18FXX20 — 25 ns
PIC18LFXX20 — 45 ns V
DD = 2.0V
79 TSCF SCK Output Fall Time (Master mode) — 25 ns
80 TSCH2DOV,
T
SCL2DOV
SDO Data Output Valid after SCK
Edge
PIC18FXX20 — 50 ns
PIC18LFXX20 — 100 ns V
DD = 2.0V
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
81
71 72
74
75, 76
78
80
MSb
79
73
MSb In
bit 6 - - - - - -1
LSb In
bit 6 - - - -1
LSb
Note: Refer to Figure 26-6 for load conditions.