Datasheet

PIC18F6520/8520/6620/8620/6720/8720
DS39609C-page 328  2003-2013 Microchip Technology Inc.
TABLE 26-14: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F8X20)
FIGURE 26-16: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
Param
No.
Symbol Characteristic Min Max Units Conditions
62 T
DTV2WRH Data In Valid before WR  or CS 
(setup time)
20
25
—
—
ns
ns Extended Temp. range
63 T
WRH2DTIWR  or CS  to Data–In
Invalid (hold time)
PIC18FXX20 20 — ns
PIC18LFXX20 35 — ns
VDD = 2.0V
64 T
RDL2DTVRD  and CS  to Data–Out Valid —
—
80
90
ns
ns Extended Temp. range
65 T
RDH2DTIRD  or CS  to Data–Out Invalid 10 30 ns
66 T
IBFINH Inhibit of the IBF flag bit being cleared from
WR
 or CS 
—3 T
CY
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73
74
75, 76
78
79
80
79
78
MSb LSb
bit 6 - - - - - -1
MSb In
LSb In
bit 6 - - - -1
Note: Refer to Figure 26-6 for load conditions.