Datasheet

PIC18F6520/8520/6620/8620/6720/8720
DS39609C-page 322  2003-2013 Microchip Technology Inc.
TABLE 26-8: CLKO AND I/O TIMING REQUIREMENTS
FIGURE 26-9: PROGRAM MEMORY READ TIMING DIAGRAM
Param
No.
Symbol Characteristic Min Typ Max Units Conditions
10 T
OSH2CKLOSC1  to CLKO  — 75 200 ns (Note 1)
11 T
OSH2CKHOSC1  to CLKO  — 75 200 ns (Note 1)
12 T
CKR CLKO Rise Time — 35 100 ns (Note 1)
13 T
CKF CLKO Fall Time — 35 100 ns (Note 1)
14 T
CKL2IOVCLKO  to Port Out Valid — — 0.5 TCY + 20 ns (Note 1)
15 T
IOV2CKH Port In Valid before CLKO  0.25 TCY + 25 — — ns (Note 1)
16 T
CKH2IOI Port In Hold after CLKO  0——ns(Note 1)
17 T
OSH2IOVOSC1  (Q1 cycle) to Port Out Valid — 50 150 ns
18 T
OSH2IOIOSC1  (Q2 cycle) to Port
Input Invalid (I/O in hold time)
PIC18FXX20 100 — — ns
18A PIC18LFXX20 200 — — ns V
DD = 2.0V
19 T
IOV2OSH Port Input Valid to OSC1 (I/O in setup time) 0 — — ns
20 T
IOR Port Output Rise Time PIC18FXX20 — 10 25 ns
20A PIC18LFXX20 — — 60 ns V
DD = 2.0V
21 T
IOF Port Output Fall Time PIC18FXX20 — 10 25 ns
21A PIC18LFXX20 — — 60 ns V
DD = 2.0V
22† T
INP INT pin High or Low Time TCY ——ns
23† T
RBP RB7:RB4 Change INT High or Low Time TCY ——ns
24† T
RCP RC7:RC4 Change INT High or Low Time 20 — — ns
† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x T
OSC.
Q1 Q2 Q3 Q4 Q1 Q2
OSC1
(1)
ALE
OE
Address Data from External
166
160
165
161
151
162
163
AD<15:0>
167
168
155
Address
Address
150
A<19:16>
Address
169
BA0
CE
171
171A
164
Operating Conditions: 2.0V < V
CC < 5.5V, -40°C < TA < +125°C unless otherwise stated.
Note 1: Maximum speed of F
OSC is 25 MHz for external program memory read.