Datasheet
2003-2013 Microchip Technology Inc. DS39609C-page 321
PIC18F6520/8520/6620/8620/6720/8720
TABLE 26-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V)
FIGURE 26-8: CLKO AND I/O TIMING
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
—FOSC Oscillator Frequency Range 4 — 10 MHz HS mode
—FSYS On-Chip VCO System Frequency 16 — 40 MHz HS mode
—t
rc
PLL Start-up Time (Lock Time) — — 2 ms
— CLK CLKO Stability (Jitter) -2 — +2 %
† Data in “Typ” column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note: Refer to Figure 26-6 for load conditions.
OSC1
CLKO
I/O pin
(Input)
I/O pin
(Output)
Q4
Q1
Q2 Q3
10
13
14
17
20, 21
19
18
15
11
12
16
Old Value
New Value