Datasheet

 2003-2013 Microchip Technology Inc. DS39609C-page 253
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 23-2: WAKE-UP FROM SLEEP THROUGH INTERRUPT
(1,2)
23.4 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC
®
devices. The user program memory is divided on
binary boundaries into individual blocks, each of which
has three separate code protection bits associated with
it:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
The code protection bits are located in Configuration
Registers 5L through 7H. Their locations within the
registers are summarized in Table 23-3.
In the PIC18FXX20 family, the block size varies with
the size of the user program memory. For PIC18FX520
devices, program memory is divided into four blocks of
8 Kbytes each. The first block is further divided into a
boot block of 2 Kbytes and a second block (Block 0) of
6 Kbytes, for a total of five blocks. The organization of
the blocks and their associated code protection bits are
shown in Figure 23-3.
For PIC18FX620 and PIC18FX720 devices, program
memory is divided into blocks of 16 Kbytes. The first
block is further divided into a boot block of 512 bytes
and a second block (Block 0) of 15.5 Kbytes, for a total
of nine blocks. This produces five blocks for 64-Kbyte
devices and nine for 128-Kbyte devices. The organiza-
tion of the blocks and their associated code protection
bits are shown in Figure 23-4.
TABLE 23-3: SUMMARY OF CODE PROTECTION REGISTERS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKO
(4)
INT pin
INTF flag
(INTCON<1>)
GIEH bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
PC PC+2 PC+4
Inst(PC) = Sleep
Inst(PC - 1)
Inst(PC + 2)
Sleep
Processor in
Sleep
Interrupt Latency
(3)
Inst(PC + 4)
Inst(PC + 2)
Inst(0008h)
Inst(000Ah)
Inst(0008h)
Dummy Cycle
PC + 4 0008h 000Ah
Dummy Cycle
T
OST
(2)
PC+4
Note 1: XT, HS or LP Oscillator mode assumed.
2: GIE = 1 assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
3: T
OST = 1024 TOSC (drawing not to scale). This delay will not occur for RC and EC Oscillator modes.
4: CLKO is not available in these oscillator modes, but shown here for timing reference.
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
300008h CONFIG5L CP7
(1)
CP6
(1)
CP5
(1)
CP4
(1)
CP3 CP2 CP1 CP0
300009h CONFIG5H CPD CPB
— — — — — —
30000Ah CONFIG6L WRT7
(1)
WRT6
(1)
WRT5
(1)
WRT4
(1)
WRT3 WRT2 WRT1 WRT0
30000Bh CONFIG6H WRTD WRTB WRTC
— — — — —
30000Ch CONFIG7L EBTR7
(1)
EBTR6
(1)
EBTR5
(1)
EBTR4
(1)
EBTR3 EBTR2 EBTR1 EBTR0
30000Dh CONFIG7H
— EBTRB — — — — — —
Legend: Shaded cells are unimplemented.
Note 1: Unimplemented in PIC18FX520 and PIC18FX620 devices.