Datasheet

 2003-2013 Microchip Technology Inc. DS39609C-page 205
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 18-2: ASYNCHRONOUS TRANSMISSION
FIGURE 18-3: ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
TABLE 18-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Word 1
Stop bit
Word 1
Transmit Shift Reg
Start bit bit 0 bit 1 bit 7/8
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC6/TX1/CK1 (pin)
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Transmit Shift Reg.
Write to TXREG
BRG Output
(Shift Clock)
RC6/TX1/CK1 (pin)
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Word 2
Word 1
Word 2
Start bit
Stop bit
Start bit
Transmit Shift Reg.
Word 1
Word 2
bit 0 bit 1
bit 7/8 bit 0
Note: This timing diagram shows two consecutive transmissions.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000
PIR1
PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1
PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111
PIR3
— — RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000
PIE3
— — RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000
IPR3
— — RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111
RCSTAx
(1)
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
TXREGx
(1)
USART Transmit Register 0000 0000 0000 0000
TXSTAx
(1)
CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
SPBRGx
(1)
Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Note 1: Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’
indicates the particular module. Bit names and Reset values are identical between modules.