Datasheet

PIC18F6520/8520/6620/8620/6720/8720
DS39609C-page 20  2003-2013 Microchip Technology Inc.
PORTJ is a bidirectional I/O port
(5)
.
RJ0/ALE
RJ0
ALE
—62
I/O
O
ST
TTL
Digital I/O.
External memory address latch enable.
RJ1/OE
RJ1
OE
—61
I/O
O
ST
TTL
Digital I/O.
External memory output enable.
RJ2/WRL
RJ2
WRL
—60
I/O
O
ST
TTL
Digital I/O.
External memory write low control.
RJ3/WRH
RJ3
WRH
—59
I/O
O
ST
TTL
Digital I/O.
External memory write high control.
RJ4/BA0
RJ4
BA0
—39
I/O
O
ST
TTL
Digital I/O.
External memory Byte Address 0 control.
RJ5/CE
RJ5
CE
—40
I/O
O
ST
TTL
Digital I/O.
External memory chip enable control.
RJ6/LB
RJ6
LB
—41
I/O
O
ST
TTL
Digital I/O.
External memory low byte select.
RJ7/UB
RJ7
UB
—42
I/O
O
ST
TTL
Digital I/O.
External memory high byte select.
VSS 9, 25,
41, 56
11, 31,
51, 70
P — Ground reference for logic and I/O pins.
V
DD 10, 26,
38, 57
12, 32,
48, 71
P — Positive supply for logic and I/O pins.
AV
SS
(6)
20 26 P — Ground reference for analog modules.
AV
DD
(6)
19 25 P — Positive supply for analog modules.
TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
PIC18F6X20 PIC18F8X20
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AV
DD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.