Datasheet

PIC18F6520/8520/6620/8620/6720/8720
DS39609C-page 16  2003-2013 Microchip Technology Inc.
PORTE is a bidirectional I/O port.
RE0/RD
/AD8
RE0
RD
AD8
(3)
24
I/O
I
I/O
ST
TTL
TTL
Digital I/O.
Read control for Parallel Slave Port
(see W
R and CS pins).
External memory address/data 8.
RE1/WR
/AD9
RE1
WR
AD9
(3)
13
I/O
I
I/O
ST
TTL
TTL
Digital I/O.
Write control for Parallel Slave Port
(see C
S and RD pins).
External memory address/data 9.
RE2/CS
/AD10
RE2
CS
AD10
(3)
64 78
I/O
I
I/O
ST
TTL
TTL
Digital I/O.
Chip select control for Parallel Slave
Port (see RD
and WR).
External memory address/data 10.
RE3/AD11
RE3
AD11
(3)
63 77
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 11.
RE4/AD12
RE4
AD12
62 76
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 12.
RE5/AD13
RE5
AD13
(3)
61 75
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 13.
RE6/AD14
RE6
AD14
(3)
60 74
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 14.
RE7/CCP2/AD15
RE7
CCP2
(1,4)
AD15
(3)
59 73
I/O
I/O
I/O
ST
ST
TTL
Digital I/O.
Capture2 input/Compare2 output/
PWM2 output.
External memory address/data 15.
TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
PIC18F6X20 PIC18F8X20
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AV
DD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.