Datasheet

 2003-2013 Microchip Technology Inc. DS39609C-page 155
PIC18F6520/8520/6620/8620/6720/8720
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
EQUATION 16-3:
16.4.3 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2
register.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
5. Configure the CCP1 module for PWM operation.
TABLE 16-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
TABLE 16-4: REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
FOSC
FPWM
---------------


log
2log
----------------------------- b i t s=
PWM Resolution (max)
PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)1641111
PR2 Value FFh FFh FFh 3Fh 1Fh 17h
Maximum Resolution (bits) 14  10 12  10 10 8 7 6.58
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000
RCON IPEN
— — RI TO PD POR BOR 0--1 11qq 0--q qquu
PIR1
PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1
PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111
PIR2
— CMIE — EEIE BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 ---0 0000
PIE2
— CMIF — EEIF BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 ---0 0000
IPR2
— CMIP — EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 ---1 1111
PIR3
— — RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000
PIE3
— — RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000
IPR3
— — RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111
TMR2 Timer2 Module Register 0000 0000 0000 0000
PR2 Timer2 Module Period Register 1111 1111 1111 1111
T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
T3CON
RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
TMR4 Timer4 Register 0000 0000 uuuu uuuu
PR4 Timer4 Period Register 1111 1111 uuuu uuuu
T4CON
— T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 uuuu uuuu
CCPRxL
(1)
Capture/Compare/PWM Register x (LSB) xxxx xxxx uuuu uuuu
CCPRxH
(1)
Capture/Compare/PWM Register x (MSB) xxxx xxxx uuuu uuuu
CCPxCON
(1)
— — DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, – = unimplemented, read as
‘0’. Shaded cells are not used by PWM, Timer2, or Timer4.
Note 1: Generic term for all of the identical registers of this name for all CCP modules, where ‘x’ identifies the individual module
(CCP1 through CCP5). Bit assignments and Reset values for all registers of the same generic name are identical.