Datasheet

PIC18F6520/8520/6620/8620/6720/8720
DS39609C-page 152  2003-2013 Microchip Technology Inc.
16.3 Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against either the TMR1 register
pair value or the TMR3 register pair value. When a
match occurs, the CCP1 pin:
• is driven High
• is driven Low
• toggles output (high-to-low or low-to-high)
• remains unchanged
The action on the pin is based on the value of control
bits, CCP1M3:CCP1M0. At the same time, interrupt
flag bit CCP1IF (CCP2IF) is set.
16.3.1 CCP PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
16.3.2 TIMER1/TIMER3 MODE SELECTION
Timer1 and/or Timer3 must be running in Timer mode,
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
16.3.3 SOFTWARE INTERRUPT MODE
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
16.3.4 SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of either CCP1 or
CCP2, resets the TMR1 or TMR3 register pair, depend-
ing on which timer resource is currently selected. This
allows the CCPR1 register to effectively be a 16-bit
programmable period register for Timer1 or Timer3.
The CCP2 Special Event Trigger will also start an A/D
conversion if the A/D module is enabled.
FIGURE 16-3: COMPARE MODE OPERATION BLOCK DIAGRAM
Note: Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to
the default low level. This is not the
PORTC I/O data latch.
Note: The special event trigger from the CCP2
module will not set the Timer1 or Timer3
interrupt flag bits.
CCPR1H CCPR1L
TMR1H TMR1L
Comparator
QS
R
Output
Logic
Special Event Trigger
Set Flag bit CCP1IF
Match
RC2/CCP1 pin
TRISC<2>
CCP1CON<3:0>
Mode Select
Output Enable
For CCP1 and CCP2 only, the Special Event Trigger will:
Reset Timer1 or Timer3, but not set Timer1 or Timer3 interrupt flag bit
and set bit GO/DONE
(ADCON0<2>),
which starts an A/D conversion (CCP2 only)
TMR3H TMR3L
T3CCP2
1
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