Datasheet

PIC18F6520/8520/6620/8620/6720/8720
DS39609C-page 120  2003-2013 Microchip Technology Inc.
10.7 PORTG, TRISG and LATG
Registers
PORTG is a 5-bit wide, bidirectional port. The corre-
sponding data direction register is TRISG. Setting a
TRISG bit (= 1) will make the corresponding PORTG
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISG bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATG) is also memory
mapped. Read-modify-write operations on the LATG
register, read and write the latched output value for
PORTG.
PORTG is multiplexed with both CCP and USART
functions (Table 10-13). PORTG pins have Schmitt
Trigger input buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings.
The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write of the TRIS register,
without concern due to peripheral overrides.
EXAMPLE 10-7: INITIALIZING PORTG
FIGURE 10-16: PORTG BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
Note: On a Power-on Reset, these pins are
configured as digital inputs.
CLRF PORTG ; Initialize PORTG by
; clearing output
; data latches
CLRF LATG ; Alternate method
; to clear output
; data latches
MOVLW 0x04 ; Value used to
; initialize data
; direction
MOVWF TRISG ; Set RG1:RG0 as outputs
; RG2 as input
; RG4:RG3 as inputs
PORTG/Peripheral Out Select
Data Bus
WR LATG
WR TRISG
Data Latch
TRIS Latch
RD TRISG
QD
Q
CK
QD
EN
Peripheral Data Out
0
1
QD
Q
CK
P
N
V
DD
VSS
RD PORTG
Peripheral Data In
I/O pin
(1)
or
WR PORTG
RD LATG
Schmitt
Trigger
Note 1: I/O pins have diode protection to V
DD and VSS.
2: Peripheral Output Enable is only active if Peripheral Select is active.
TRIS
Override
Peripheral Output
Logic
TRIS OVERRIDE
Pin Override Peripheral
RG0 Yes CCP3 I/O
RG1 Yes USART1 Async
Xmit, Sync Clock
RG2 Yes USART1 Async
Rcv, Sync Data
Out
RG3 Yes CCP4 I/O
RG4 Yes CCP5 I/O
Enable
(2)