Datasheet

 2003-2013 Microchip Technology Inc. DS39609C-page 109
PIC18F6520/8520/6620/8620/6720/8720
10.3 PORTC, TRISC and LATC
Registers
PORTC is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register, read and write the latched output value for
PORTC.
PORTC is multiplexed with several peripheral functions
(Table 10-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings.
The pin override value is not loaded into the TRIS
register. This allows read-modify-write of the TRIS
register, without concern due to peripheral overrides.
RC1 is normally configured by configuration bit,
CCP2MX, as the default peripheral pin of the CCP2
module (default/erased state, CCP2MX = 1).
EXAMPLE 10-3: INITIALIZING PORTC
FIGURE 10-8: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
Note: On a Power-on Reset, these pins are
configured as digital inputs.
CLRF PORTC ; Initialize PORTC by
; clearing output
; data latches
CLRF LATC ; Alternate method
; to clear output
; data latches
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISC ; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
PORTC/Peripheral Out Select
Data Bus
WR LATC
WR TRISC
Data Latch
TRIS Latch
RD TRISC
QD
Q
CK
QD
EN
Peripheral Data Out
0
1
QD
Q
CK
P
N
V
DD
VSS
RD PORTC
Peripheral Data In
I/O pin
(1)
or
WR PORTC
RD LATC
Schmitt
Trigger
Note 1: I/O pins have diode protection to V
DD and VSS.
2: Peripheral Output Enable is only active if Peripheral Select is active.
TRIS
Override
Peripheral Output
Logic
TRIS OVERRIDE
Pin Override Peripheral
RC0 Yes Timer1 Osc for
Timer1/Timer3
RC1 Yes Timer1 Osc for
Timer1/Timer3,
CCP2 I/O
RC2 Yes CCP1 I/O
RC3 Yes SPI/I
2
C
Master Clock
RC4 Yes I
2
C Data Out
RC5 Yes SPI Data Out
RC6 Yes USART1 Async
Xmit, Sync Clock
RC7 Yes USART1 Sync
Data Out
Enable
(2)