Datasheet

PIC18F6520/8520/6620/8620/6720/8720
DS39609C-page 104  2003-2013 Microchip Technology Inc.
FIGURE 10-2: BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
FIGURE 10-3: BLOCK DIAGRAM OF
RA4/T0CKI PIN
FIGURE 10-4: BLOCK DIAGRAM OF RA6 PIN (WHEN ENABLED AS I/O)
Data
Bus
QD
Q
CK
QD
Q
CK
QD
EN
P
N
WR LATA
WR TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
V
SS
VDD
I/O pin
(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
Analog
Input
Mode
TTL
Input
Buffer
To A/D Converter and LVD Modules
RD LATA
or
PORTA
Data
Bus
WR TRISA
RD PORTA
Data Latch
TRIS Latch
Schmitt
Trigger
Input
Buffer
N
V
SS
I/O pin
(1)
TMR0 Clock Input
QD
Q
CK
QD
Q
CK
EN
QD
EN
RD LATA
WR LATA
or
PORTA
Note 1: I/O pins have protection diodes to V
DD and VSS.
RD TRISA
Data Bus
Q
D
Q
CK
QD
EN
P
N
WR LATA
WR
Data Latch
TRIS Latch
RD
RD PORTA
V
SS
VDD
I/O pin
(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
or
PORTA
RD LATA
ECRA6 or
TTL
Input
Buffer
ECRA6 or RCRA6 Enable
RCRA6 Enable
TRISA
Q
D
Q
CK
TRISA