Datasheet

PIC18F6520/8520/6620/8620/6720/8720
DS39609C-page 100  2003-2013 Microchip Technology Inc.
REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5 RC2IP: USART2 Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4 TX2IP: USART2 Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3 TMR4IP: TMR4 to PR4 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2-0 CCPxIP: CCPx Interrupt Priority bit (CCP Modules 3, 4 and 5)
1 = High priority
0 = Low priority
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown