Datasheet

PIC18F6520/8520/6620/8620/6720/8720
DS39609C-page 10  2003-2013 Microchip Technology Inc.
FIGURE 1-2: PIC18F8X20 BLOCK DIAGRAM
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKI
OSC2/CLKO
MCLR
/VPP
VDD, VSS
PORTA
PORTB
PORTC
RA4/T0CKI
RA5/AN4/LVDIN
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX1/CK1
RC7/RX1/DT1
Brown-out
Reset
USART1
Comparator
Synchronous
BOR
Serial Port
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
Timing
Generation
10-bit
A/D
Data Latch
Data RAM
Address Latch
Address<12>
12
Bank0, F
BSR
FSR0
FSR1
FSR2
inc/dec
logic
Decode
4
12 4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
WREG
8
BITOP
8
8
ALU<8>
8
Address Latch
Program Memory
Data Latch
21
21
16
8
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
PORTD
RD7/PSP7/AD7:
PCLATU
PCU
Precision
Reference
Band Gap
PORTE
PORTF
PORTG
RG0/CCP3
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4
RG4/CCP5
RF7/SS
RE6/AD14
RE7/CCP2/AD15
RE5/AD13
RE4/AD12
RE3/AD11
RE2/CS/AD10
RE0/RD/AD8
RE1/WR/AD9
LVD
PORTH
PORTJ
RJ0/ALE
RJ1/OE
RJ2/WRL
RJ3/WRH
RA6
Timer0
Timer1
Timer2
Timer3
Timer4
CCP1 CCP2 CCP3 CCP4 CCP5
USART2
System Bus Interface
AD15:AD0, A19:A16
(1)
Note 1: External memory interface pins are physically multiplexed with PORTD (AD7:AD0), PORTE (AD15:AD8) and PORTH (A19:A16).
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3/CCP2
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
RH7/AN15:RH4/AN12
RH3/AD19:RH0/AD16
RJ4/BA0
RJ5/CE
RJ6/LB
RJ7/UB
RF6/AN11
RF5/AN10/CVREF
RF4/AN9
RF3/AN8
RF2/AN7/C1OUT
RF0/AN5
RF1/AN6/C2OUT
Data
EEPROM
RD0/PSP0/AD0