PIC18F6520/8520/6620/ 8620/6720/8720 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D High-Performance RISC CPU: Analog Features: • C compiler optimized architecture/instruction set: - Source code compatible with the PIC16 and PIC17 instruction sets • Linear program memory addressing to 128 Kbytes • Linear data memory addressing to 3840 bytes • 1 Kbyte of data EEPROM • Up to 10 MIPs operation: - DC – 40 MHz osc./clock input - 4 MHz – 10 MHz osc.
PIC18F6520/8520/6620/8620/6720/8720 Pin Diagrams Note 1: RE5 RE6 RE7/CCP2(1) RD0/PSP0 VDD VSS RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 61 60 58 56 55 54 53 52 51 50 49 RD6/PSP6 RD7/PSP7 RE4 57 RE3 62 59 RE2/CS 64 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PIC18F6520 PIC18F6620 PIC18F6720 RB2/INT2 RB3/INT3 RB4/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC VSS OSC2/CLKO/RA6 OSC1/CLKI VDD RB7/KBI3/PGD RC5/SDO RC4/SDI/SDA RC3/SCK/SCL RC2/CCP1 32 RA5/AN4/LVDIN 31 27 28 VDD 30 26 VSS
PIC18F6520/8520/6620/8620/6720/8720 Pin Diagrams (Continued) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RH1/A17 RH0/A16 RE2/CS/AD10(3) RE3/AD11 RE4/AD12 RE5/AD13 RE6/AD14 RE7/CCP2/AD15(2) RD0/PSP0/AD0(3) VDD VSS RD1/PSP1/AD1(3) RD2/PSP2/AD2(3) RD3/PSP3/AD3(3) RD4/PSP4/AD4(3) RD5/PSP5/AD5(3) RD6/PSP6/AD6(3) RD7/PSP7/AD7(3) RJ0/ALE RJ1/OE 80-Pin TQFP RH2/A18 RH3/A19 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIC18F8520 PIC18F8620 PIC18F8720 60 59 58 57 56 55 54 53 52 51 50 49 48 47
PIC18F6520/8520/6620/8620/6720/8720 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Oscillator Configurations ............................................................................................................................................................ 21 3.0 Reset .................................................................
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PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 6 2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720 1.0 DEVICE OVERVIEW This document contains device specific information for the following devices: • PIC18F6520 • PIC18F8520 • PIC18F6620 • PIC18F8620 • PIC18F6720 • PIC18F8720 This family offers the same advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price – with the addition of high endurance Enhanced Flash program memory.
PIC18F6520/8520/6620/8620/6720/8720 1.2 Details on Individual Family Members 3. 4. The PIC18FXX20 devices are available in 64-pin and 80-pin packages. They are differentiated from each other in five ways: 1. 2. 5.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 1-1: PIC18F6X20 BLOCK DIAGRAM Data Bus<8> 21 Table Pointer<21> RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/LVDIN RA6 Data Latch 8 21 PORTA 8 Data RAM inc/dec logic Address Latch 21 PCLATU PCLATH PCU PCH PCL Program Counter 12 4 4 Bank0, F FSR0 FSR1 FSR2 31 Level Stack Program Memory RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3 RB4/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD Address<12> BSR Address Latch PORTB 12 12 Data Latch inc/de
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 1-2: PIC18F8X20 BLOCK DIAGRAM Data Bus<8> 21 Table Pointer<21> RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/LVDIN RA6 Data Latch 8 21 PORTA 8 Data RAM inc/dec logic System Bus Interface Address Latch 21 PCLATU PCLATH PCU PCH PCL Program Counter 12 4 4 Bank0, F FSR0 FSR1 FSR2 31 Level Stack Program Memory RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3/CCP2 RB4/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD Address<12> BSR Address Latch PORT
PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS Pin Number Pin Name MCLR/VPP Pin PIC18F6X20 PIC18F8X20 Type 7 9 I MCLR ST P VPP OSC1/CLKI OSC1 Buffer Type 39 49 I CMOS/ST I CMOS O — CLKO O — RA6 I/O TTL CLKI OSC2/CLKO/RA6 OSC2 40 50 Description Master Clear (input) or programming voltage (output). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Oscillator crystal or external clock input.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Type PIC18F6X20 PIC18F8X20 Buffer Type Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 24 RA1/AN1 RA1 AN1 23 RA2/AN2/VREFRA2 AN2 VREF- 22 RA3/AN3/VREF+ RA3 AN3 VREF+ 21 RA4/T0CKI RA4 28 30 RA6 27 TTL Analog Digital I/O. Analog input 0. I/O I TTL Analog Digital I/O. Analog input 1. I/O I I TTL Analog Analog Digital I/O. Analog input 2.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Type PIC18F6X20 PIC18F8X20 Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Type PIC18F6X20 PIC18F8X20 Buffer Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 30 RC1/T1OSI/CCP2 RC1 T1OSI CCP2(2) 29 RC2/CCP1 RC2 CCP1 33 RC3/SCK/SCL RC3 SCK 34 36 35 RC5/SDO RC5 SDO 36 RC6/TX1/CK1 RC6 TX1 CK1 31 RC7/RX1/DT1 RC7 RX1 DT1 32 ST — ST Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Type PIC18F6X20 PIC18F8X20 Buffer Type Description PORTD is a bidirectional I/O port. These pins have TTL input buffers when external memory is enabled.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Type PIC18F6X20 PIC18F8X20 Buffer Type Description PORTE is a bidirectional I/O port. RE0/RD/AD8 RE0 RD 2 4 AD8(3) RE1/WR/AD9 RE1 WR 1 64 RE3/AD11 RE3 AD11(3) RE4/AD12 RE4 AD12 62 RE5/AD13 RE5 AD13(3) 61 RE6/AD14 RE6 AD14(3) 60 RE7/CCP2/AD15 RE7 CCP2(1,4) 59 AD15(3) Digital I/O. Read control for Parallel Slave Port (see WR and CS pins). External memory address/data 8.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Type PIC18F6X20 PIC18F8X20 Buffer Type Description PORTF is a bidirectional I/O port. RF0/AN5 RF0 AN5 18 RF1/AN6/C2OUT RF1 AN6 C2OUT 17 RF2/AN7/C1OUT RF2 AN7 C1OUT 16 RF3/AN8 RF1 AN8 15 RF4/AN9 RF1 AN9 14 RF5/AN10/CVREF RF1 AN10 CVREF 13 RF6/AN11 RF6 AN11 12 RF7/SS RF7 SS 11 24 I/O I ST Analog Digital I/O. Analog input 5. I/O I O ST Analog ST Digital I/O.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Type PIC18F6X20 PIC18F8X20 Buffer Type Description PORTG is a bidirectional I/O port. RG0/CCP3 RG0 CCP3 3 RG1/TX2/CK2 RG1 TX2 CK2 4 RG2/RX2/DT2 RG2 RX2 DT2 5 RG3/CCP4 RG3 CCP4 6 RG4/CCP5 RG4 CCP5 8 5 I/O I/O ST ST Digital I/O. Capture3 input/Compare3 output/ PWM3 output. I/O O I/O ST — ST Digital I/O. USART 2 asynchronous transmit.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Type PIC18F6X20 PIC18F8X20 Buffer Type Description PORTH is a bidirectional I/O port(5). RH0/A16 RH0 A16 — RH1/A17 RH1 A17 — RH2/A18 RH2 A18 — RH3/A19 RH3 A19 — RH4/AN12 RH4 AN12 — RH5/AN13 RH5 AN13 — RH6/AN14 RH6 AN14 — RH7/AN15 RH7 AN15 — 79 I/O O ST TTL Digital I/O. External memory address 16. I/O O ST TTL Digital I/O. External memory address 17.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 1-2: PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Type PIC18F6X20 PIC18F8X20 Buffer Type Description PORTJ is a bidirectional I/O port(5). RJ0/ALE RJ0 ALE — RJ1/OE RJ1 OE — RJ2/WRL RJ2 WRL — RJ3/WRH RJ3 WRH — RJ4/BA0 RJ4 BA0 — RJ5/CE RJ5 CE — RJ6/LB RJ6 LB — RJ7/UB RJ7 UB — 62 I/O O ST TTL Digital I/O. External memory address latch enable. I/O O ST TTL Digital I/O. External memory output enable.
PIC18F6520/8520/6620/8620/6720/8720 2.0 OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types TABLE 2-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS Ranges Tested: Mode The PIC18FXX20 devices can be operated in eight different oscillator modes. The user can program three configuration bits (FOSC2, FOSC1 and FOSC0) to select one of these eight modes: 1. 2. 3. 4. LP XT HS HS+PLL 5. 6. RC RCIO 7. 8. EC ECIO 2.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR FIGURE 2-2: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION) Ranges Tested: Mode Freq LP 32 kHz 200 kHz XT 1 MHz 4 MHz HS C1 C2 15-22 pF 15-22 pF 15-22 pF 15-22 pF 8 MHz 15-22 pF 15-22 pF PIC18FXX20 OSC2 Open 2.3 4 MHz OSC1 Clock from Ext. System RC Oscillator See the notes following this table for additional information.
PIC18F6520/8520/6620/8620/6720/8720 2.4 FIGURE 2-5: External Clock Input The EC and ECIO Oscillator modes require an external clock source to be connected to the OSC1 pin. The feedback device between OSC1 and OSC2 is turned off in these modes to save current. There is a maximum 1.5 s start-up required after a Power-on Reset, or wake-up from Sleep mode. In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin.
PIC18F6520/8520/6620/8620/6720/8720 2.6 Oscillator Switching Feature execution mode. Figure 2-7 shows a block diagram of the system clock sources. The clock switching feature is enabled by programming the Oscillator Switching Enable (OSCSEN) bit in Configuration Register 1H to a ‘0’. Clock switching is disabled in an erased device. See Section 12.0 “Timer1 Module” for further details of the Timer1 oscillator. See Section 23.0 “Special Features of the CPU” for Configuration register details.
PIC18F6520/8520/6620/8620/6720/8720 2.6.1 SYSTEM CLOCK SWITCH BIT Note: The system clock source switching is performed under software control. The system clock switch bit, SCS (OSCCON<0>), controls the clock switching. When the SCS bit is ‘0’, the system clock source comes from the main oscillator that is selected by the FOSC configuration bits in Configuration Register 1H. When the SCS bit is set, the system clock source will come from the Timer1 oscillator. The SCS bit is cleared on all forms of Reset.
PIC18F6520/8520/6620/8620/6720/8720 2.6.2 OSCILLATOR TRANSITIONS A timing diagram indicating the transition from the main oscillator to the Timer1 oscillator is shown in Figure 2-8. The Timer1 oscillator is assumed to be running all the time. After the SCS bit is set, the processor is frozen at the next occurring Q1 cycle. After eight synchronization cycles are counted from the Timer1 oscillator, operation resumes. No additional delays are required after the synchronization cycles.
PIC18F6520/8520/6620/8620/6720/8720 frequency. A timing diagram, indicating the transition from the Timer1 oscillator to the main oscillator for HS-PLL mode, is shown in Figure 2-10. If the main oscillator is configured for HS-PLL mode, an oscillator start-up time (TOST), plus an additional PLL time-out (TPLL), will occur.
PIC18F6520/8520/6620/8620/6720/8720 2.7 Effects of Sleep Mode on the On-Chip Oscillator When the device executes a SLEEP instruction, the onchip clocks and oscillator are turned off and the device is held at the beginning of an instruction cycle (Q1 state). With the oscillator off, the OSC1 and OSC2 signals will stop oscillating. Since all the transistor switching currents have been removed, Sleep mode achieves the lowest current consumption of the device (only leakage currents).
PIC18F6520/8520/6620/8620/6720/8720 3.0 RESET The PIC18FXX20 devices various kinds of Reset: a) b) c) d) e) f) g) h) differentiate between Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during Sleep Watchdog Timer (WDT) Reset (during normal operation) Programmable Brown-out Reset (PBOR) RESET Instruction Stack Full Reset Stack Underflow Reset Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation.
PIC18F6520/8520/6620/8620/6720/8720 3.1 Power-on Reset (POR) A Power-on Reset pulse is generated on-chip when VDD rise is detected. To take advantage of the POR circuitry, tie the MCLR pin through a 1 k to 10 k resistor to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (parameter D004). For a slow rise time, see Figure 3-2. When the device starts normal operation (i.e.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 3-1: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) Oscillator Configuration Brown-out Wake-up from Sleep or Oscillator Switch PWRTE = 0 PWRTE = 1 HS with PLL enabled(1) 72 ms + 1024 TOSC + 2ms 1024 TOSC + 2 ms 72 ms(2) + 1024 TOSC + 2 ms 1024 TOSC + 2 ms HS, XT, LP 72 ms + 1024 TOSC 1024 TOSC 72 ms(2) + 1024 TOSC 1024 TOSC 72 ms 1.5 s EC External RC Note 1: 2: 3: 72 ms — 72 ms (2) 1.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt ---0 0000 ---0 uuuu(3) TOSH PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu(3) TOSL PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu(3) STKPTR PIC18F6X20 PIC18F8X20 00-0 0000 uu-0 0000 uu-u uuuu(3) PCLATU PIC18F6X20 PIC18F8X20 ---0 0000 ---0 0000 ---u uuuu PCLATH P
PIC18F6520/8520/6620/8620/6720/8720 TABLE 3-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt FSR1H PIC18F6X20 PIC18F8X20 ---- xxxx ---- uuuu ---- uuuu FSR1L PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu BSR PIC18F6X20 PIC18F8X20 ---- 0000 ---- 0000 ---- uuuu INDF2 PIC18F6X20 PIC18F8X20 N/A N/A N/A POSTINC2 PIC18F6X20 PIC18F8X20 N/A N/A N/A POSTDEC
PIC18F6520/8520/6620/8620/6720/8720 TABLE 3-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt ADRESH PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 PIC18F6X20 PIC18F8X20 --00 0000 --00 0000 --uu uuuu ADCON1 PIC18F6X20 PIC18F8X20 --00 0000 --00 0000 --uu uuuu ADCON2 PIC18F6X20 PIC18F8X
PIC18F6520/8520/6620/8620/6720/8720 TABLE 3-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt IPR3 PIC18F6X20 PIC18F8X20 --11 1111 --11 1111 --uu uuuu PIR3 PIC18F6X20 PIC18F8X20 --00 0000 --00 0000 --uu uuuu PIE3 PIC18F6X20 PIC18F8X20 --00 0000 --00 0000 --uu uuuu IPR2 PIC18F6X20 PIC18F8X20 -1-1 1111 -1-1 1111 -u-u uuuu PIR2 PIC18F6X20 PIC18F8X20 -0-0 00
PIC18F6520/8520/6620/8620/6720/8720 TABLE 3-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt PORTJ PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu PORTH PIC18F6X20 PIC18F8X20 0000 xxxx 0000 uuuu uuuu uuuu PORTG PIC18F6X20 PIC18F8X20 ---x xxxx uuuu uuuu ---u uuuu PORTF PIC18F6X20 PIC18F8X20 x000 0000 u000 0000 u000 0000 PORTE PIC18F6X20 PIC18F8X20 xx
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 3-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD VIA 1 k RESISTOR) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 FIGURE 3-4: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 3-5: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 2003-2
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 3-6: SLOW RISE TIME (MCLR TIED TO VDD VIA 1 kRESISTOR) 5V VDD 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD VIA 1 kRESISTOR) VDD MCLR IINTERNAL POR TPWRT PWRT TIME-OUT OST TIME-OUT TOST TPLL PLL TIME-OUT INTERNAL RESET Note: DS39609C-page 38 TOST = 1024 clock cycles. TPLL 2 ms max. First three stages of the PWRT timer.
PIC18F6520/8520/6620/8620/6720/8720 4.0 MEMORY ORGANIZATION There are three memory blocks in PIC18FXX20 devices. They are: • Program Memory • Data RAM • Data EEPROM Data and program memory use separate busses, which allows for concurrent access of these blocks. Additional detailed information for Flash program memory and data EEPROM is provided in Section 5.0 “Flash Program Memory” and Section 7.0 “Data EEPROM Memory”, respectively.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 4-1: INTERNAL PROGRAM MEMORY MAP AND STACK FOR PIC18FXX20 DEVICES PC<20:0> CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1 21 Stack Level 31 000000h 000000h 000000h Reset Vector 000008h 000008h 000008h High Priority Interrupt Vector 000018h 000018h 000018h Low Priority Interrupt Vector On-Chip Flash Program Memory On-Chip Flash Program Memory 00FFFFh 010000h On-Chip Flash Program Memory User Memory Space 007FFFh 008000h 01FFFFh 020000h Rea
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 4-1: CONFIG3L CONFIGURATION BYTE R/P-1 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1 WAIT — — — — — PM1 PM0 bit 7 bit 0 bit 7 WAIT: External Bus Data Wait Enable bit 1 = Wait selections unavailable, device will not wait 0 = Wait programmed by WAIT1 and WAIT0 bits of MEMCOM register (MEMCOM<5:4>) bit 6-2 Unimplemented: Read as ‘0’ bit 1-0 PM1:PM0: Processor Data Memory Mode Select bits 11 = Microcontroller mode 10 = Microprocessor mode 01 = Microcontroll
PIC18F6520/8520/6620/8620/6720/8720 4.2 Return Address Stack The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a CALL or RCALL instruction is executed, or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions.
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 4-2: STKPTR REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SP4 SP3 SP2 SP1 SP0 STKFUL(1) STKUNF(1) bit 7 bit 0 bit 7 STKFUL: Stack Full Flag bit 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 SP4:SP0: Stack Pointer Location bits Note 1: Bit 7 and bit 6 can
PIC18F6520/8520/6620/8620/6720/8720 4.3 Fast Register Stack 4.4 A “fast interrupt return” option is available for interrupts. A Fast Register Stack is provided for the Status, WREG and BSR registers and is only one in depth. The stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt.
PIC18F6520/8520/6620/8620/6720/8720 4.6 Instruction Flow/Pipelining A fetch cycle begins with the program counter (PC) incrementing in Q1. An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined, such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.
PIC18F6520/8520/6620/8620/6720/8720 4.7.1 TWO-WORD INSTRUCTIONS The PIC18FXX20 devices have four two-word instructions: MOVFF, CALL, GOTO and LFSR. The second word of these instructions has the 4 MSBs set to ‘1’s and is a special kind of NOP instruction. The lower 12 bits of the second word contain data to be used by the instruction. If the first word of the instruction is executed, the data in the second word is accessed.
PIC18F6520/8520/6620/8620/6720/8720 4.9 Data Memory Organization The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The data memory map is in turn divided into 16 banks of 256 bytes each. The lower 4 bits of the Bank Select Register (BSR<3:0>) select which bank will be accessed. The upper 4 bits of the BSR are not implemented.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 4-6: DATA MEMORY MAP FOR PIC18FX520 DEVICES BSR<3:0> = 0000 = 0001 = 0010 Data Memory Map = 0110 = 0111 Access RAM FFh 00h GPRs 000h 05Fh 060h 0FFh 100h GPRs Bank 1 FFh 00h Bank 2 1FFh 200h GPRs 2FFh 300h FFh 00h = 0011 00h Bank 0 Bank 3 to Bank 6 GPRs Access Bank FFh 00h Bank 7 6FFh 700h GPRs FFh 7FFh 800h 00h 5Fh Access RAM High 60h (SFRs) FFh Access RAM Low = 1000 Unused, Read as ‘0’ Bank 8 to Bank 14 = 1110 = 1111 00h
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 4-7: DATA MEMORY MAP FOR PIC18FX620 AND PIC18FX720 DEVICES BSR<3:0> = 0000 = 0001 = 0010 = 0011 Data Memory Map 00h Access RAM FFh 00h GPRs Bank 0 GPRs Bank 1 FFh 00h Bank 2 1FFh 200h GPRs 2FFh 300h FFh 00h Bank 3 GPRs FFh = 0100 Bank 4 3FFh 400h GPRs Access Bank 4FFh 500h = 0101 000h 05Fh 060h 0FFh 100h Bank 5 to Bank 13 GPRs = 1101 = 1110 = 1111 00h 5Fh Access RAM High 60h (SFRs) FFh Access RAM Low DFFh E00h 00h Bank 14 GPRs
PIC18F6520/8520/6620/8620/6720/8720 TABLE 4-2: SPECIAL FUNCTION REGISTER MAP Address Name FFFh Address TOSU FFEh FDFh TOSH FDEh Name Address (3) Name Address Name FBFh CCPR1H F9Fh IPR1 POSTINC2(3) FBEh CCPR1L F9Eh PIR1 (3) F9Dh PIE1 INDF2 FFDh TOSL FBDh CCP1CON FFCh STKPTR FDCh FDDh POSTDEC2 PREINC2(3) FBCh CCPR2H F9Ch MEMCON(2) FFBh PCLATU FDBh PLUSW2(3) FBBh CCPR2L F9Bh —(1) FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah TRISJ FF9h PCL FD9h FSR2L FB9
PIC18F6520/8520/6620/8620/6720/8720 TABLE 4-2: Address SPECIAL FUNCTION REGISTER MAP (CONTINUED) Name Address Name —(1) Name Address Name — F7Eh — (1) F5Eh — F7Dh —(1) F5Dh —(1) F3Dh —(1) F1Dh —(1) F7Ch — (1) F5Ch — (1) F3Ch — (1) F1Ch —(1) F7Bh —(1) F5Bh —(1) F3Bh —(1) F1Bh —(1) F7Ah — (1) F5Ah — (1) F3Ah — (1) F1Ah —(1) F79h —(1) F59h —(1) F39h —(1) F19h —(1) (1) F38h — (1) F18h —(1) F7Fh F5Fh Address (1) F3Fh —(1) F1Fh —(1) (1) F3E
PIC18F6520/8520/6620/8620/6720/8720 TABLE 4-3: File Name TOSU REGISTER FILE SUMMARY Bit 7 Bit 6 Bit 5 — — — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Top-of-Stack Upper Byte (TOS<20:16>) Value on Details POR, BOR on page: ---0 0000 32, 42 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 32, 42 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 32, 42 Return Stack Pointer 00-0 0000 32, 43 Holding Register for PC<20:16> --10 0000 32, 44 STKPTR STKFUL STKUNF — PCLATU — — bit 21 PCLATH H
PIC18F6520/8520/6620/8620/6720/8720 TABLE 4-3: File Name REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details POR, BOR on page: PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) n/a 57 PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – value of FSR2 offset by value in WREG n/a 57 ---- 0000 33, 57 FSR2H FSR2L STATUS — —
PIC18F6520/8520/6620/8620/6720/8720 TABLE 4-3: File Name REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details POR, BOR on page: CCPR3H Capture/Compare/PWM Register 3 High Byte xxxx xxxx 34, 151, 152 CCPR3L Capture/Compare/PWM Register 3 Low Byte xxxx xxxx 34, 151, 152 CCP3CON — — DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 --00 0000 34, 149 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 34, 229 C2OUT C1OUT C2INV C1
PIC18F6520/8520/6620/8620/6720/8720 TABLE 4-3: File Name REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 LATJ(3) Read PORTJ Data Latch, Write PORTJ Data Latch LATH(3) Read PORTH Data Latch, Write PORTH Data Latch LATG — — — Bit 3 Bit 2 Bit 1 Bit 0 Value on Details POR, BOR on page: xxxx xxxx 35, 125 xxxx xxxx 35, 122 Read PORTG Data Latch, Write PORTG Data Latch ---x xxxx 35, 120 LATF Read PORTF Data Latch, Write PORTF Data Latch xxxx xxxx 35, 117 LATE Read PORTE Data Latc
PIC18F6520/8520/6620/8620/6720/8720 4.10 Access Bank 4.11 The Access Bank is an architectural enhancement, which is very useful for C compiler code optimization. The techniques used by the C compiler may also be useful for programs written in assembly. The need for a large general purpose memory space dictates a RAM banking scheme. The data memory is partitioned into sixteen banks. When using direct addressing, the BSR should be configured for the desired bank.
PIC18F6520/8520/6620/8620/6720/8720 4.12 Indirect Addressing, INDF and FSR Registers Indirect addressing is a mode of addressing data memory, where the data memory address in the instruction is not fixed. An FSR register is used as a pointer to the data memory location that is to be read or written. Since this pointer is in RAM, the contents can be modified by the program. This can be useful for data tables in the data memory and for software stacks. Figure 4-9 shows the operation of indirect addressing.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 4-9: INDIRECT ADDRESSING OPERATION RAM 0h Instruction Executed Opcode Address FFFh 12 File Address = Access of an Indirect Addressing Register BSR<3:0> Instruction Fetched 4 Opcode FIGURE 4-10: 12 12 8 FSR File INDIRECT ADDRESSING Indirect Addressing 11 FSR Register 0 Location Select 0000h Data Memory(1) 0FFFh Note 1: DS39609C-page 58 For register file map detail, see Table 4-2. 2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720 4.13 Status Register The Status register, shown in Register 4-3, contains the arithmetic status of the ALU. The Status register can be the destination for any instruction, as with any other register. If the Status register is the destination for an instruction that affects the Z, DC, C, OV or N bits, then the write to these five bits is disabled. These bits are set or cleared according to the device logic.
PIC18F6520/8520/6620/8620/6720/8720 4.14 RCON Register Note 1: If the BOREN configuration bit is set (Brown-out Reset enabled), the BOR bit is ‘1’ on a Power-on Reset. After a Brownout Reset has occurred, the BOR bit will be cleared and must be set by firmware to indicate the occurrence of the next Brown-out Reset. The Reset Control (RCON) register contains flag bits that allow differentiation between the sources of a device Reset. These flags include the TO, PD, POR, BOR and RI bits.
PIC18F6520/8520/6620/8620/6720/8720 5.0 FLASH PROGRAM MEMORY The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces through an 8-bit register (TABLAT). The Flash program memory is readable, writable and erasable, during normal operation over the entire VDD range. Table read operations retrieve data from program memory and place it into the data RAM space.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 5-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: 5.2 Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the Program Memory Array is discussed in Section 5.5 “Writing to Flash Program Memory”.
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 5-1: EECON1 REGISTER (ADDRESS FA6h) R/W-x EEPGD bit 7 R/W-x CFGS U-0 — R/W-0 FREE R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-0 RD bit 0 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash R
PIC18F6520/8520/6620/8620/6720/8720 5.2.2 TABLAT – TABLE LATCH REGISTER 5.2.4 The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch is used to hold 8-bit data during data transfers between program memory and data RAM. 5.2.3 TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the Table Pointer determine which byte is read from program memory into TABLAT.
PIC18F6520/8520/6620/8620/6720/8720 5.3 Reading the Flash Program Memory TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. FIGURE 5-4: The internal program memory is typically organized by words.
PIC18F6520/8520/6620/8620/6720/8720 5.4 5.4.1 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. The sequence of events for erasing a block of internal program memory location is: 1. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased.
PIC18F6520/8520/6620/8620/6720/8720 5.5 Writing to Flash Program Memory The minimum programming block is 4 words or 8 bytes. Word or byte programming is not supported. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 8 holding registers used by the table writes for programming. Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction has to be executed 8 times for each programming operation.
PIC18F6520/8520/6620/8620/6720/8720 EXAMPLE 5-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D’64 COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL TBLRD*+ MOVF MOVWF DECFSZ BRA TABLAT, W POSTINC0 COUNTER READ_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF DATA_ADDR_HIGH FSR0H DATA_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ; number of bytes in erase
PIC18F6520/8520/6620/8620/6720/8720 EXAMPLE 5-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BSF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF NOP BSF DECFSZ BRA BCF Required Sequence 5.5.
PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 70 2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720 6.0 Note: EXTERNAL MEMORY INTERFACE 6.1 The External Memory Interface is not implemented on PIC18F6X20 (64-pin) devices. The External Memory Interface is a feature of the PIC18F8X20 devices that allows the controller to access external memory devices (such as Flash, EPROM, SRAM, etc.) as program or data memory. The physical implementation of the interface uses 27 pins.
PIC18F6520/8520/6620/8620/6720/8720 If the device fetches or accesses external memory while EBDIS = 1, the pins will switch to external bus. If the EBDIS bit is set by a program executing from external memory, the action of setting the bit will be delayed until the program branches into the internal memory. At that time, the pins will change from external bus to I/O ports.
PIC18F6520/8520/6620/8620/6720/8720 6.2 16-bit Mode The External Memory Interface implemented in PIC18F8X20 devices operates only in 16-bit mode. The mode selection is not software configurable, but is programmed via the configuration bits. The WM<1:0> bits in the MEMCON register determine three types of connections in 16-bit mode.
PIC18F6520/8520/6620/8620/6720/8720 6.2.2 16-BIT WORD WRITE MODE Figure 6-2 shows an example of 16-bit Word Write mode for PIC18F8X20 devices. This mode is used for word-wide memories, which includes some of the EPROM and Flash type memories. This mode allows opcode fetches and table reads from all forms of 16-bit memory and table writes to any type of word-wide external memories. This method makes a distinction between TBLWT cycles to even or odd addresses.
PIC18F6520/8520/6620/8620/6720/8720 6.2.3 16-BIT BYTE SELECT MODE Figure 6-3 shows an example of 16-bit Byte Select mode for PIC18F8X20 devices. This mode allows table write operations to word-wide external memories with byte selection capability. This generally includes both word-wide Flash and SRAM devices. During a TBLWT cycle, the TABLAT data is presented on the upper and lower byte of the AD15:AD0 bus. The WRH signal is strobed for each write cycle; the WRL pin is not used.
PIC18F6520/8520/6620/8620/6720/8720 6.2.4 16-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 6-4 through Figure 6-6.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 6-6: EXTERNAL MEMORY BUS TIMING FOR SLEEP (MICROPROCESSOR MODE) Q1 Q2 Q4 Q1 Q2 3AAAh Q3 Q4 Q1 00h 00h A<19:16> AD<15:0> Q3 0003h 3AABh 0E55h CE ALE OE Memory Cycle Instruction Execution Opcode Fetch SLEEP from 007554h Opcode Fetch MOVLW 55h from 007556h INST(PC-2) SLEEP 2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 78 2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720 7.0 DATA EEPROM MEMORY The data EEPROM is readable and writable during normal operation over the entire VDD range. The data memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFR). There are five SFRs used to read and write the program and data EEPROM memory. These registers are: • • • • • EECON1 EECON2 EEDATA EEADRH EEADR The EEPROM data memory allows byte read and write.
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 7-1: EECON1 REGISTER (ADDRESS FA6h) R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Flash Program/Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access configuration or calibration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’
PIC18F6520/8520/6620/8620/6720/8720 7.3 Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADRH:EEADR register pair, clear the EEPGD control bit (EECON1<7>), clear the CFGS EXAMPLE 7-1: MOVLW MOVWF MOVLW MOVWF BCF BCF BSF MOVF 7.4 control bit (EECON1<6>) and then set the RD control bit (EECON1<0>). The data is available for the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction.
PIC18F6520/8520/6620/8620/6720/8720 7.5 Write Verify 7.8 Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 7.6 Protection Against Spurious Write There are conditions when the user may not want to write to the data EEPROM memory.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 7-1: Name INTCON EEADRH REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Bit 7 Bit 6 Bit 5 Bit 4 GIE/GIEH PEIE/GIEL TMR0IE INT0IE — — — — Bit 3 Bit 2 RBIE TMR0IF — — Bit 1 Bit 0 INT0IF RBIF EE Addr Register High Value on POR, BOR Value on all other Resets 0000 0000 0000 0000 ---- --00 ---- --00 EEADR EEPROM Address Register 0000 0000 0000 0000 EEDATA EEPROM Data Register 0000 0000 0000 0000 EECON2 EEPROM Control Register 2 (not a physi
PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 84 2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720 8.0 8 X 8 HARDWARE MULTIPLIER 8.1 Introduction 8.2 Example 8-1 shows the sequence to do an 8 x 8 unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register. An 8 x 8 hardware multiplier is included in the ALU of the PIC18FXX20 devices. By making the multiply a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that gives a 16-bit result.
PIC18F6520/8520/6620/8620/6720/8720 Example 8-3 shows the sequence to do a 16 x 16 unsigned multiply. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers, RES3:RES0.
PIC18F6520/8520/6620/8620/6720/8720 9.0 INTERRUPTS The PIC18FXX20 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high or a low priority level. The high priority interrupt vector is at 000008h, while the low priority interrupt vector is at 000018h. High priority interrupt events will override any low priority interrupts that may be in progress. There are thirteen registers which are used to control interrupt operation.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 9-1: INTERRUPT LOGIC TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE Wake-up if in Sleep mode Interrupt to CPU Vector to Location 0008h INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit GIEH/GIE TMR1IF TMR1IE TMR1IP IPEN IPEN XXXXIF XXXXIE XXXXIP GIEL/PEIE IPEN Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation Per
PIC18F6520/8520/6620/8620/6720/8720 9.1 INTCON Registers Note: The INTCON registers are readable and writable registers, which contain various enable, priority and flag bits. REGISTER 9-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 9-2: INTCON2 REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = In
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 9-3: INTCON3 REGISTER R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF bit 7 bit 0 bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 INT3IE: INT3 External Interrupt Enable bit 1 = Enables the INT3 external interrupt 0 = Disables the INT3 external interrupt bi
PIC18F6520/8520/6620/8620/6720/8720 9.2 PIR Registers Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Flag Registers (PIR1, PIR2 and PIR3).
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CMIF — EEIF BCLIF LVDIF TMR3IF CCP2IF bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 CMIF: Comparator Interrupt Flag bit 1 = The comparator input has changed (must be cleared in software) 0 = The comparator input has not changed bit 5 Unimplemented: Read as ‘0’ bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit 1 = Th
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 U-0 U-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF bit 7 bit 0 bit 7- 6 Unimplemented: Read as ‘0’ bit 5 RC2IF: USART2 Receive Interrupt Flag bit 1 = The USART2 receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The USART2 receive buffer is empty bit 4 TX2IF: USART2 Transmit Interrupt Flag bit 1 = The USART2 transmit buffer, TXREG, is em
PIC18F6520/8520/6620/8620/6720/8720 9.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2 and PIE3). When the IPEN bit (RCON<7>) is ‘0’, the PEIE bit must be set to enable any of these peripheral interrupts.
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CMIE — EEIE BCLIE LVDIE TMR3IE CCP2IE bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enables the comparator interrupt 0 = Disables the comparator interrupt bit 5 Unimplemented: Read as ‘0’ bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit 1 = Enables the write operation interrupt 0
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 9-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IE: USART2 Receive Interrupt Enable bit 1 = Enables the USART2 receive interrupt 0 = Disables the USART2 receive interrupt bit 4 TX2IE: USART2 Transmit Interrupt Enable bit 1 = Enables the USART2 transmit interrupt 0 = Disables the USART2 transmit i
PIC18F6520/8520/6620/8620/6720/8720 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority Registers (IPR1, IPR2 and IPR3). The operation of the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 9-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 U-0 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — CMIP — EEIP BCLIP LVDIP TMR3IP CCP2IP bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 BCLIP: Bus Collision Interrupt Pr
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IP: USART2 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX2IP: USART2 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 TMR4IP: TMR4 to PR4 Match Interrupt Priority bit 1 = High priority 0 = Low
PIC18F6520/8520/6620/8620/6720/8720 9.5 RCON Register The RCON register contains the IPEN bit, which is used to enable prioritized interrupts. The functions of the other bits in this register are discussed in more detail in Section 4.14 “RCON Register”.
PIC18F6520/8520/6620/8620/6720/8720 9.6 INT0 Interrupt 9.7 External interrupts on the RB0/INT0, RB1/INT1, RB2/INT2 and RB3/INT3 pins are edge-triggered: either rising, if the corresponding INTEDGx bit is set in the INTCON2 register, or falling, if the INTEDGx bit is clear. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxE.
PIC18F6520/8520/6620/8620/6720/8720 10.0 I/O PORTS 10.1 Depending on the device selected, there are either seven or nine I/O ports available on PIC18FXX20 devices. Some of their pins are multiplexed with one or more alternate functions from the other peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 10-2: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS FIGURE 10-3: BLOCK DIAGRAM OF RA4/T0CKI PIN RD LATA RD LATA Data Bus D WR LATA or PORTA Data Bus WR LATA or PORTA Q VDD CK Q P WR TRISA N Q I/O pin(1) WR TRISA CK Q CK Q N Data Latch Data Latch D D VSS Analog Input Mode Q TRIS Latch D Q CK Q I/O pin(1) VSS Schmitt Trigger Input Buffer TRIS Latch RD TRISA RD TRISA Q D TTL Input Buffer Q D ENEN EN RD PORTA RD PORTA TMR0 Clock Input
PIC18F6520/8520/6620/8620/6720/8720 TABLE 10-1: PORTA FUNCTIONS Name RA0/AN0 Bit# Buffer bit 0 TTL Function Input/output or analog input. RA1/AN1 bit 1 TTL Input/output or analog input. RA2/AN2/VREF- bit 2 TTL Input/output or analog input or VREF-. RA3/AN3/VREF+ bit 3 TTL Input/output or analog input or VREF+. RA4/T0CKI bit 4 ST Input/output or external clock input for Timer0. Output is open-drain type.
PIC18F6520/8520/6620/8620/6720/8720 10.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 10-6: BLOCK DIAGRAM OF RB2:RB0 PINS VDD RBPU(2) Weak P Pull-up Data Latch D Q Data Bus I/O pin(1) WR Port CK TRIS Latch D WR TRIS Q TTL Input Buffer CK RD TRIS Q D RD Port EN INTx RD Port Schmitt Trigger Buffer Note FIGURE 10-7: 1: 2: I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
PIC18F6520/8520/6620/8620/6720/8720 TABLE 10-3: PORTB FUNCTIONS Name Bit# Buffer RB0/INT0 bit 0 TTL/ST(1) Input/output pin or external interrupt input 0. Internal software programmable weak pull-up. RB1/INT1 bit 1 TTL/ST(1) Input/output pin or external interrupt input 1. Internal software programmable weak pull-up. RB2/INT2 bit 2 TTL/ST(1) Input/output pin or external interrupt input 2. Internal software programmable weak pull-up.
PIC18F6520/8520/6620/8620/6720/8720 10.3 PORTC, TRISC and LATC Registers The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register, without concern due to peripheral overrides. PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode).
PIC18F6520/8520/6620/8620/6720/8720 TABLE 10-5: PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T13CKI bit 0 ST Input/output port pin, Timer1 oscillator output or Timer1/Timer3 clock input. RC1/T1OSI/CCP2(1) bit 1 ST Input/output port pin, Timer1 oscillator input or Capture2 input/ Compare2 output/PWM output (when CCP2MX configuration bit is disabled). RC2/CCP1 bit 2 ST Input/output port pin or Capture1 input/Compare1 output/ PWM1 output.
PIC18F6520/8520/6620/8620/6720/8720 10.4 PORTD, TRISD and LATD Registers PORTD can also be configured as an 8-bit wide microprocessor port (Parallel Slave Port) by setting control bit PSPMODE (TRISE<4>). In this mode, the input buffers are TTL. See Section 10.10 “Parallel Slave Port” for additional information on the Parallel Slave Port (PSP). PORTD is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISD.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 10-10: PORTD BLOCK DIAGRAM IN SYSTEM BUS MODE Q D EN EN RD PORTD RD LATD Data Bus D WR LATD or PORTD CK Q Port Data I/O pin(1) 0 1 Data Latch D WR TRISD Q CK TRIS Latch TTL Input Buffer RD TRISD Bus Enable System Bus Data/TRIS Out Control Drive Bus Instruction Register Instruction Read Note 1: I/O pins have protection diodes to VDD and VSS. DS39609C-page 112 2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 10-7: PORTD FUNCTIONS Name Bit# Buffer Type Function RD0/PSP0/AD0 bit 0 ST/TTL(1) Input/output port pin, Parallel Slave Port bit 0 or address/data bus bit 0. bit 1 ST/TTL (1) Input/output port pin, Parallel Slave Port bit 1 or address/data bus bit 1. ST/TTL (1) Input/output port pin, Parallel Slave Port bit 2 or address/data bus bit 2. ST/TTL (1) Input/output port pin, Parallel Slave Port bit 3 or address/data bus bit 3.
PIC18F6520/8520/6620/8620/6720/8720 10.5 PORTE, TRISE and LATE Registers PORTE is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin).
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 10-11: PORTE BLOCK DIAGRAM IN I/O MODE Peripheral Out Select Peripheral Data Out VDD 0 P RD LATE 1 Data Bus WR LATE or WR PORTE D Q CK Q Data Latch WR TRISE D Q CK Q I/O pin(1) N TRIS OVERRIDE VSS TRIS Override TRIS Latch RD TRISE Schmitt Trigger Peripheral Enable Q D EN RD PORTE Peripheral Data In Pin Override Peripheral RE0 Yes External Bus RE1 Yes External Bus RE2 Yes External Bus RE3 Yes External Bus RE4 Yes External B
PIC18F6520/8520/6620/8620/6720/8720 TABLE 10-9: PORTE FUNCTIONS Name Bit# Buffer Type RE0/RD/AD8 bit 0 ST/TTL(1) Input/output port pin, read control for Parallel Slave Port or address/data bit 8 For RD (PSP Control mode): 1 = Not a read operation 0 = Read operation, reads PORTD register (if chip selected) RE1/WR/AD9 bit 1 ST/TTL(1) Input/output port pin, write control for Parallel Slave Port or address/data bit 9 For WR (PSP Control mode): 1 = Not a write operation 0 = Write operation, writes PO
PIC18F6520/8520/6620/8620/6720/8720 10.6 EXAMPLE 10-6: PORTF, LATF and TRISF Registers PORTF is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISF. Setting a TRISF bit (= 1) will make the corresponding PORTF pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISF bit (= 0) will make the corresponding PORTF pin an output (i.e., put the contents of the output latch on the selected pin).
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 10-14: RF6:RF3 AND RF0 PINS BLOCK DIAGRAM D WR LATF or WR PORTF D WR LATF or WR PORTF CK Q VDD CK Data Bus Q P D VSS Analog Input Mode Q TRIS Latch Q Schmitt Trigger Input Buffer I/O pin WR TRISF CK I/O pin D N Q Q Data Latch Data Latch WR TRISF RF7 PIN BLOCK DIAGRAM RD LATF RD LATF Data Bus FIGURE 10-15: CK TRIS Latch TTL Input Buffer RD TRISF RD TRISF ST Input Buffer Q Q D D ENEN EN RD PORTF RD PORTF SS Input To A/D Converter
PIC18F6520/8520/6620/8620/6720/8720 TABLE 10-11: PORTF FUNCTIONS Name Bit# Buffer Type Function RF0/AN5 bit 0 ST Input/output port pin or analog input. RF1/AN6/C2OUT bit 1 ST Input/output port pin, analog input or comparator 2 output. RF2/AN7/C1OUT bit 2 ST Input/output port pin, analog input or comparator 1 output. RF3/AN8 bit 3 ST Input/output port pin or analog input/comparator input. RF4/AN9 bit 4 ST Input/output port pin or analog input/comparator input.
PIC18F6520/8520/6620/8620/6720/8720 10.7 PORTG, TRISG and LATG Registers make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. PORTG is a 5-bit wide, bidirectional port. The corresponding data direction register is TRISG. Setting a TRISG bit (= 1) will make the corresponding PORTG pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISG bit (= 0) will make the corresponding PORTC pin an output (i.e.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 10-13: PORTG FUNCTIONS Name Bit# Buffer Type Function RG0/CCP3 bit 0 ST Input/output port pin or Capture3 input/Compare3 output/PWM3 output. RG1/TX2/CK2 bit 1 ST Input/output port pin, addressable USART2 asynchronous transmit or addressable USART2 synchronous clock. RG2/RX2/DT2 bit 2 ST Input/output port pin, addressable USART2 asynchronous receive or addressable USART2 synchronous data.
PIC18F6520/8520/6620/8620/6720/8720 10.8 Note: PORTH, LATH and TRISH Registers PORTH is available only on PIC18F8X20 devices. FIGURE 10-17: RD LATH PORTH is an 8-bit wide, bidirectional I/O port. The corresponding data direction register is TRISH. Setting a TRISH bit (= 1) will make the corresponding PORTH pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISH bit (= 0) will make the corresponding PORTH pin an output (i.e.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 10-19: RH3:RH0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE Q D EN EN RD PORTH RD LATD Data Bus WR LATH or PORTH D Q Port I/O pin(1) 0 Data 1 CK Data Latch D WR TRISH Q CK TRIS Latch TTL Input Buffer RD TRISH External Enable System Bus Control Address Out Drive System To Instruction Register Instruction Read Note 1: I/O pins have diode protection to VDD and VSS. 2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 10-15: PORTH FUNCTIONS Name Bit# Buffer Type bit 0 ST/TTL(1) Input/output port pin or address bit 16 for external memory interface. bit 1 ST/TTL(1) Input/output port pin or address bit 17 for external memory interface. RH2/A18 bit 2 ST/TTL (1) Input/output port pin or address bit 18 for external memory interface. RH3/A19 bit 3 ST/TTL(1) Input/output port pin or address bit 19 for external memory interface.
PIC18F6520/8520/6620/8620/6720/8720 10.9 Note: PORTJ, TRISJ and LATJ Registers PORTJ is available only on PIC18F8X20 devices. FIGURE 10-20: RD LATJ PORTJ is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISJ. Setting a TRISJ bit (= 1) will make the corresponding PORTJ pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISJ bit (= 0) will make the corresponding PORTJ pin an output (i.e.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 10-21: RJ4:RJ0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE Q D ENEN RD PORTJ RD LATJ Data Bus D Data WR LATJ or PORTJ I/O pin(1) Port 0 Q 1 CK Data Latch D WR TRISJ Q CK TRIS Latch RD TRISJ Control Out System Bus Control External Enable Drive System Note 1: I/O pins have diode protection to VDD and VSS.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 10-17: PORTJ FUNCTIONS Name Bit# Buffer Type Function RJ0/ALE bit 0 ST Input/output port pin or address latch enable control for external memory interface. RJ1/OE bit 1 ST Input/output port pin or output enable control for external memory interface. RJ2/WRL bit 2 ST Input/output port pin or write low byte control for external memory interface. RJ3/WRH bit 3 ST Input/output port pin or write high byte control for external memory interface.
PIC18F6520/8520/6620/8620/6720/8720 10.10 Parallel Slave Port PORTD also operates as an 8-bit wide Parallel Slave Port, or microprocessor port, when control bit PSPMODE (PSPCON<4>) is set. It is asynchronously readable and writable by the external world through the RD control input pin, RE0/RD/AD8 and the WR control input pin, RE1/WR/AD9. Note: For PIC18F8X20 devices, the Parallel Slave Port is available only in Microcontroller mode. The PSP can directly interface to an 8-bit microprocessor data bus.
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 10-1: PSPCON REGISTER R-0 R-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 IBF OBF IBOV PSPMODE — — — — bit 7 bit 0 bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit 1 = A write occurred when
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 10-25: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 10-19: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets PORTD Port Data Latch when written; Port pins when read xxxx xxxx uuuu uuuu LATD LATD Data Output bits xxxx xxxx uuuu uuuu TRISD PORTD Data Direction bits 1111 1111
PIC18F6520/8520/6620/8620/6720/8720 11.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 11-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE Data Bus FOSC/4 0 8 0 1 RA4/T0CKI pin Programmable Prescaler 1 Sync with Internal Clocks TMR0 (2 TCY delay) T0SE 3 PSA Set Interrupt Flag bit TMR0IF on Overflow T0PS2, T0PS1, T0PS0 T0CS Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
PIC18F6520/8520/6620/8620/6720/8720 11.1 11.2.1 Timer0 Operation Timer0 can operate as a timer or as a counter. The prescaler assignment is fully under software control, (i.e., it can be changed “on-the-fly” during program execution). Timer mode is selected by clearing the T0CS bit. In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles.
PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 134 2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720 12.0 TIMER1 MODULE The Timer1 module timer/counter has the following features: • 16-bit timer/counter (two 8-bit registers: TMR1H and TMR1L) • Readable and writable (both registers) • Internal or external clock select • Interrupt-on-overflow from FFFFh to 0000h • Reset from CCP module special event trigger Register 12-1 details the Timer1 Control register.
PIC18F6520/8520/6620/8620/6720/8720 12.1 Timer1 Operation When TMR1CS = 0, Timer1 increments every instruction cycle. When TMR1CS = 1, Timer1 increments on every rising edge of the external clock input or the Timer1 oscillator, if enabled. Timer1 can operate in one of these modes: • As a timer • As a synchronous counter • As an asynchronous counter When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins become inputs.
PIC18F6520/8520/6620/8620/6720/8720 12.2 12.2.1 Timer1 Oscillator A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit, T1OSCEN (T1CON<3>). The oscillator is a low-power oscillator, rated up to 200 kHz. It will continue to run during Sleep. It is primarily intended for a 32 kHz crystal. The circuit for a typical LP oscillator is shown in Figure 12-3. Table 12-1 shows the capacitor selection for the Timer1 oscillator.
PIC18F6520/8520/6620/8620/6720/8720 12.3 Timer1 Interrupt The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 Interrupt Enable bit, TMR1IE (PIE1<0>). 12.
PIC18F6520/8520/6620/8620/6720/8720 EXAMPLE 12-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BSF RETURN 0x80 TMR1H TMR1L b’00001111’ T1OSC secs mins .12 hours PIE1, TMR1IE BSF BCF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN MOVLW MOVWF RETURN TMR1H, 7 PIR1, TMR1IF secs, F .
PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 140 2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720 13.0 TIMER2 MODULE 13.1 Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is readable and writable and is cleared on any device Reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits, T2CKPS1:T2CKPS0 (T2CON<1:0>).
PIC18F6520/8520/6620/8620/6720/8720 13.2 Timer2 Interrupt 13.3 The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. FIGURE 13-1: Output of TMR2 The output of TMR2 (before the postscaler) is fed to the synchronous serial port module, which optionally uses it to generate the shift clock.
PIC18F6520/8520/6620/8620/6720/8720 14.0 TIMER3 MODULE Figure 14-1 is a simplified block diagram of the Timer3 module. The Timer3 module timer/counter has the following features: • 16-bit timer/counter (two 8-bit registers; TMR3H and TMR3L) • Readable and writable (both registers) • Internal or external clock select • Interrupt-on-overflow from FFFFh to 0000h • Reset from CCP module trigger REGISTER 14-1: Register 14-1 shows the Timer3 Control register.
PIC18F6520/8520/6620/8620/6720/8720 14.1 Timer3 Operation When TMR3CS = 0, Timer3 increments every instruction cycle. When TMR3CS = 1, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. Timer3 can operate in one of these modes: • As a timer • As a synchronous counter • As an asynchronous counter When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins become inputs.
PIC18F6520/8520/6620/8620/6720/8720 14.2 Timer1 Oscillator 14.4 The Timer1 oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting the T1OSCEN (T1CON<3>) bit. The oscillator is a lowpower oscillator rated up to 200 kHz. See Section 12.0 “Timer1 Module” for further details. 14.3 If the CCP module is configured in Compare mode to generate a “special event trigger” (CCP1M3:CCP1M0 = 1011), this signal will reset Timer3.
PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 146 2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720 15.0 TIMER4 MODULE 15.1 The Timer4 module timer has the following features: • • • • • • 8-bit timer (TMR4 register) 8-bit period register (PR4) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR4 match of PR4 Timer4 has a control register shown in Register 15-1. Timer4 can be shut-off by clearing control bit, TMR4ON (T4CON<2>), to minimize power consumption.
PIC18F6520/8520/6620/8620/6720/8720 15.2 Timer4 Interrupt 15.3 The Timer4 module has an 8-bit period register, PR4, which is both readable and writable. Timer4 increments from 00h until it matches PR4 and then resets to 00h on the next increment cycle. The PR4 register is initialized to FFh upon Reset. FIGURE 15-1: Output of TMR4 The output of TMR4 (before the postscaler) is used only as a PWM time base for the CCP modules. It is not used as a baud rate clock for the MSSP, as is the Timer2 output.
PIC18F6520/8520/6620/8620/6720/8720 16.0 CAPTURE/COMPARE/PWM (CCP) MODULES The PIC18FXX20 devices all have five CCP (Capture/ Compare/PWM) modules. Each module contains a 16-bit register, which can operate as a 16-bit Capture register, a 16-bit Compare register or a Pulse Width Modulation (PWM) Master/Slave Duty Cycle register. Table 16-1 shows the timer resources of the CCP module modes. For the sake of clarity, CCP module operation in the following sections is described with respect to CCP1.
PIC18F6520/8520/6620/8620/6720/8720 16.1 TABLE 16-1: CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. 16.1.1 CCP MODULES AND TIMER RESOURCES The CCP modules utilize Timers 1, 2, 3 or 4, depending on the mode selected.
PIC18F6520/8520/6620/8620/6720/8720 16.2 16.2.3 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on pin RC2/CCP1. An event is defined as one of the following: • • • • every falling edge every rising edge every 4th rising edge every 16th rising edge 16.2.1 CCP PIN CONFIGURATION In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit. Note: 16.2.
PIC18F6520/8520/6620/8620/6720/8720 16.3 16.3.2 Compare Mode TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit CCPR1 register value is constantly compared against either the TMR1 register pair value or the TMR3 register pair value. When a match occurs, the CCP1 pin: Timer1 and/or Timer3 must be running in Timer mode, or Synchronized Counter mode, if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. • • • • 16.3.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 16-2: Name REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Bit 7 INTCON Bit 6 GIE/GIEH PEIE/GIEL RCON IPEN Value on POR, BOR Value on all other Resets Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 — RI TO PD POR BOR 0--1 11qq 0--q qquu — PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR
PIC18F6520/8520/6620/8620/6720/8720 16.4 16.4.1 PWM Mode In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. PWM PERIOD The PWM period is specified by writing to the PR2 register.
PIC18F6520/8520/6620/8620/6720/8720 16.4.3 The maximum PWM resolution (bits) for a given PWM frequency is given by the equation: The following steps should be taken when configuring the CCP module for PWM operation: EQUATION 16-3: 1. F OSC log --------------- F PWM PWM Resolution (max) = -----------------------------bits log 2 2. 3. Note: If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared. TABLE 16-3: 9.77 kHz 39.06 kHz 156.25 kHz 312.
PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 156 2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720 17.0 17.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC18F6520/8520/6620/8620/6720/8720 17.3.1 REGISTERS The MSSP module has four registers for SPI mode operation. These are: • • • • In receive operations, SSPSR and SSPBUF together create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set.
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 17-2: SSPCON1: MSSP CONTROL REGISTER1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit SPI Slave mode: 1 = A new byte is received while the SSP
PIC18F6520/8520/6620/8620/6720/8720 17.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
PIC18F6520/8520/6620/8620/6720/8720 17.3.3 ENABLING SPI I/O 17.3.4 To enable the serial port, SSP Enable bit, SSPEN (SSPCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins.
PIC18F6520/8520/6620/8620/6720/8720 17.3.5 MASTER MODE Figure 17-3, Figure 17-5 and Figure 17-6, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user-programmable to be one of the following: The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 17-2) is to broadcast data by the software protocol.
PIC18F6520/8520/6620/8620/6720/8720 17.3.6 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/ pull-down resistors may be desirable, depending on the application. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 cycle after Q2 SSPSR to SSPBUF FIGURE 17-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 7
PIC18F6520/8520/6620/8620/6720/8720 17.3.8 SLEEP OPERATION 17.3.10 In Master mode, all module clocks are halted and the transmission/reception will remain in that state until the device wakes from Sleep. After the device returns to normal mode, the module will continue to transmit/ receive data. Table 17-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits.
PIC18F6520/8520/6620/8620/6720/8720 17.4 I2C Mode 17.4.1 The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing.
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 17-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high-speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs bit 5 D/A
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPBUF register is written
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowle
PIC18F6520/8520/6620/8620/6720/8720 17.4.2 OPERATION The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON<5>). The SSPCON1 register allows control of the I 2C operation.
PIC18F6520/8520/6620/8620/6720/8720 17.4.3.2 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set, or bit SSPOV (SSPCON1<6>) is set.
DS39609C-page 172 CKP 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 (CKP does not reset to ‘0’ when SEN = 0) SSPOV (SSPCON<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S A7 7 A1 8 9 ACK R/W = 0 1 D7 3 4 D4 5 D3 Receiving Data D5 Cleared in software SSPBUF is read 2 D6 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 4 D4 5 D3 Receiving Data D5 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPBUF is still full. ACK is not sent.
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DS39609C-page 174 2 1 4 1 5 0 7 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 6 A9 A8 8 9 (CKP does not reset to ‘0’ when SEN = 0) UA (SSPSTAT<1>) SSPOV (SSPCON<6>) CKP 3 1 Cleared in software BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S 1 ACK R/W = 0 A7 2 4 A4 5 A3 6 8 9 A0 ACK UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address 7 A2 A1 Cleared in so
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PIC18F6520/8520/6620/8620/6720/8720 17.4.4 CLOCK STRETCHING Both 7- and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence. 17.4.4.
PIC18F6520/8520/6620/8620/6720/8720 17.4.4.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCL output is forced to ‘0’. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has FIGURE 17-12: already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL.
DS39609C-page 178 CKP SSPOV (SSPCON<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S A7 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 7 A1 8 9 ACK R/W = 0 3 4 D4 5 D3 Receiving Data D5 Cleared in software 2 D6 If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to ‘0’ and no clock stretching will occur SSPBUF is read 1 D7 6 D2 7 D1 9 ACK 1 D7 BF is set after falling edge of the 9th clock, CKP is reset to ‘0’ and clock stretching occurs 8
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PIC18F6520/8520/6620/8620/6720/8720 17.4.5 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master.
PIC18F6520/8520/6620/8620/6720/8720 MASTER MODE Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset, or when the MSSP module is disabled.
PIC18F6520/8520/6620/8620/6720/8720 17.4.6.1 I2C Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock.
PIC18F6520/8520/6620/8620/6720/8720 17.4.7 BAUD RATE GENERATOR 2 In I C Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPADD register (Figure 17-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to ‘0’ and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically.
PIC18F6520/8520/6620/8620/6720/8720 17.4.7.1 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the FIGURE 17-18: SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and begins counting.
PIC18F6520/8520/6620/8620/6720/8720 17.4.8 I2C MASTER MODE START CONDITION TIMING 17.4.8.1 If the user writes the SSPBUF when a Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). To initiate a Start condition, the user sets the Start Condition Enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and starts its count.
PIC18F6520/8520/6620/8620/6720/8720 17.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING Immediately following the setting of the SSPIF bit, the user may write the SSPBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode).
PIC18F6520/8520/6620/8620/6720/8720 17.4.10 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address, or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full flag bit, BF and allow the Baud Rate Generator to begin counting and start the next transmission.
DS39609C-page 188 S R/W PEN SEN BF (SSPSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared in software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPBUF written 1 D7 1 SCL held low while CPU responds to SSPIF ACK = 0 R/W = 0 SSPBUF written with 7-bit address and R/W, start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPBUF is written in software Cleared in software service routine from SSP interrupt 2 D6 Transmitting Da
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PIC18F6520/8520/6620/8620/6720/8720 17.4.12 ACKNOWLEDGE SEQUENCE TIMING 17.4.13 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPCON2<2>). At the end of a receive/ transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’.
PIC18F6520/8520/6620/8620/6720/8720 17.4.14 SLEEP OPERATION 17.4.17 2 While in Sleep mode, the I C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 17.4.15 EFFECT OF A RESET A Reset disables the MSSP module and terminates the current transfer. 17.4.
PIC18F6520/8520/6620/8620/6720/8720 17.4.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) SDA or SCL are sampled low at the beginning of the Start condition (Figure 17-26). SCL is sampled low before SDA is asserted low (Figure 17-27). b) During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 17-28).
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 17-27: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF.
PIC18F6520/8520/6620/8620/6720/8720 17.4.17.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 17-29). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time.
PIC18F6520/8520/6620/8620/6720/8720 17.4.17.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> and counts down to ‘0’. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 17-31).
PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 196 2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720 18.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) The Universal Synchronous Asynchronous Receiver Transmitter (USART) module (also known as a Serial Communications Interface or SCI) is one of the two types of serial I/O modules available on PIC18FXX20 devices. Each device has two USARTs, which can be configured independently of each other.
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 18-1: TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 CSRC bit 7 R/W-0 TX9 R/W-0 TXEN R/W-0 SYNC U-0 — bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care.
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 18-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER R/W-0 SPEN bit 7 R/W-0 RX9 R/W-0 SREN R/W-0 CREN R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care.
PIC18F6520/8520/6620/8620/6720/8720 18.1 USART Baud Rate Generator (BRG) Example 18-1 shows the calculation of the baud rate error for the following conditions: • • • • The BRG supports both the Asynchronous and Synchronous modes of the USARTs. It is a dedicated 8-bit Baud Rate Generator. The SPBRG register controls the period of a free running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTAx<2>) also controls the baud rate. In Synchronous mode, bit BRGH is ignored.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 18-3: BAUD RATES FOR SYNCHRONOUS MODE FOSC = 40 MHz 33 MHz BAUD RATE (Kbps) KBAUD % ERROR SPBRG value (decimal) 0.3 NA - 1.2 NA - 2.4 NA 9.6 25 MHz KBAUD % ERROR SPBRG value (decimal) - NA - - NA - - - NA NA - - 19.2 NA - - 76.8 76.92 +0.16 96 96.15 +0.16 300 303.03 +1.01 500 500 0 HIGH 10000 LOW 39.06 20 MHz KBAUD % ERROR SPBRG value (decimal) - NA - - NA - - - NA NA - - NA - - 129 77.10 +0.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 18-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) FOSC = 40 MHz 33 MHz BAUD RATE (Kbps) KBAUD % ERROR SPBRG value (decimal) 0.3 NA - 1.2 NA - 2.4 NA - 25 MHz KBAUD % ERROR SPBRG value (decimal) - NA - - NA - - 2.40 -0.07 20 MHz KBAUD % ERROR SPBRG value (decimal) - NA - - NA - 214 2.40 -0.15 KBAUD % ERROR SPBRG value (decimal) - NA - - - NA - - 162 2.40 +0.16 129 9.6 9.62 +0.16 64 9.55 -0.54 53 9.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) FOSC = 40 MHz 33 MHz BAUD RATE (Kbps) KBAUD % ERROR SPBRG value (decimal) 0.3 NA - 1.2 NA - 2.4 NA 9.6 25 MHz KBAUD % ERROR SPBRG value (decimal) - NA - - NA - - - NA NA - - 19.2 19.23 +0.16 76.8 75.76 -1.36 96 96.15 +0.16 300 312.50 +4.17 7 500 500 0 4 HIGH 2500 - 0 LOW 9.77 - 255 20 MHz KBAUD % ERROR SPBRG value (decimal) - NA - - NA - - - NA 9.
PIC18F6520/8520/6620/8620/6720/8720 18.2 USART Asynchronous Mode PIR3<4> for USART2), is set. This interrupt can be enabled/disabled by setting/clearing enable bit, TXxIE (PIE1<4> for USART1, PIE<4> for USART2). Flag bit TXxIF will be set, regardless of the state of enable bit TXxIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREGx register.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 18-2: ASYNCHRONOUS TRANSMISSION Write to TXREG BRG Output (Shift Clock) Word 1 RC6/TX1/CK1 (pin) Start bit bit 0 bit 1 TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) FIGURE 18-3: bit 7/8 Stop bit Word 1 Word 1 Transmit Shift Reg ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG Word 1 BRG Output (Shift Clock) RC6/TX1/CK1 (pin) TXIF bit (Interrupt Reg. Flag) Start bit TRMT bit (Transmit Shift Reg.
PIC18F6520/8520/6620/8620/6720/8720 18.2.2 USART ASYNCHRONOUS RECEIVER 18.2.3 The USART receiver block diagram is shown in Figure 18-4. The data is received on the pin (RC7/RX1/ DT1 or RG2/RX2/DT2) and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. To set up an Asynchronous Reception: 1.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 18-5: ASYNCHRONOUS RECEPTION Start bit bit 0 RX (pin) bit 1 Start bit bit 7/8 Stop bit Rcv Shift Reg Rcv Buffer Reg bit 0 Stop bit Start bit bit 7/8 Stop bit Word 2 RCREG Word 1 RCREG Read Rcv Buffer Reg RCREG bit 7/8 RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.
PIC18F6520/8520/6620/8620/6720/8720 18.3 USART Synchronous Master Mode In Synchronous Master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTAx<4>). In addition, enable bit SPEN (RCSTAx<7>) is set in order to configure the appropriate I/O pins to CK (clock) and DT (data) lines, respectively.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 18-6: SYNCHRONOUS TRANSMISSION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX1/DT1 pin bit 0 bit 1 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 bit 2 bit 7 Word 1 bit 0 bit 1 Word 2 bit 7 RC6/TX1/CK1 pin Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT TRMT bit TXEN bit Note: ‘1’ ‘1’ Sync Master mode; SPBRG = 0. Continuous transmission of two 8-bit words.
PIC18F6520/8520/6620/8620/6720/8720 18.3.2 USART SYNCHRONOUS MASTER RECEPTION 4. If interrupts are desired, set enable bit RCxIE in the appropriate PIE register. 5. If 9-bit reception is desired, set bit RX9. 6. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit RCxIF will be set when reception is complete and an interrupt will be generated if the enable bit RCxIE was set. 8.
PIC18F6520/8520/6620/8620/6720/8720 18.4 USART Synchronous Slave Mode To set up a Synchronous Slave Transmission: Synchronous Slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the TXx pin (RC6/TX1/CK1 or RG1/TX2/CK2), instead of being supplied internally in Master mode. TRISC<6> must be set for this mode. This allows the device to transfer or receive data while in Sleep mode. Slave mode is entered by clearing bit CSRC (TXSTAx<7>). 18.4.
PIC18F6520/8520/6620/8620/6720/8720 18.4.2 USART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical, except in the case of the Sleep mode and bit SREN, which is a “don’t care” in Slave mode. 2. 3. 4. 5. If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during Sleep.
PIC18F6520/8520/6620/8620/6720/8720 19.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The module has five registers: The analog-to-digital (A/D) converter module has 12 inputs for the PIC18F6X20 devices and 16 for the PIC18F8X20 devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number.
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 19-2: ADCON1 REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 VCFG1:VCFG0: Voltage Reference Configuration bits: VCFG1 VCFG0 A/D VREF- 00 AVDD AVSS 01 External VREF+ AVSS 10 AVDD External VREF- 11 External VREF+ External VREF- PCFG3 PCFG0 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 PCFG3:PCFG0:
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 19-3: ADCON2 REGISTER R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 ADFM — — — — ADCS2 ADCS1 ADCS0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6-3 Unimplemented: Read as ‘0’ bit 2-0 ADCS1:ADCS0: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC (clock derived from an RC oscillator = 1 MHz max) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC (clock derived fro
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 19-1: A/D BLOCK DIAGRAM CHS3:CHS0 1111 AN15(1) 1110 AN14(1) 1101 AN13(1) 1100 AN12(1) 1011 1010 1001 1000 0111 0110 0101 0100 VAIN 0011 (Input Voltage) 10-bit Converter A/D 0010 0001 VCFG1:VCFG0 0000 VDD AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VREF+ Reference Voltage VREFVSS Note 1: Channels AN15 through AN12 are not available on PIC18F6X20 devices. 2: I/O pins have diode protection to VDD and VSS.
PIC18F6520/8520/6620/8620/6720/8720 The value in the ADRESH/ADRESL registers is not modified for a Power-on Reset. The ADRESH/ ADRESL registers will contain unknown data after a Power-on Reset. 2. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 19.1 “A/D Acquisition Requirements”.
PIC18F6520/8520/6620/8620/6720/8720 19.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 19-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD).
PIC18F6520/8520/6620/8620/6720/8720 19.2 Selecting the A/D Conversion Clock 19.3 The A/D conversion time per bit is defined as TAD. The A/D conversion requires 12 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable. There are seven possible options for TAD: • • • • • • • 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC Internal RC oscillator The ADCON1, TRISA, TRISF and TRISH registers control the operation of the A/D port pins.
PIC18F6520/8520/6620/8620/6720/8720 19.4 A/D Conversions 19.5 Figure 19-3 shows the operation of the A/D converter after the GO bit has been set. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D conversion sample. That is, the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers).
PIC18F6520/8520/6620/8620/6720/8720 TABLE 19-2: SUMMARY OF A/D REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/ GIEH PEIE/ GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 01
PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 222 2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720 20.0 COMPARATOR MODULE The comparator module contains two analog comparators. The inputs to the comparators are multiplexed with the RF1 through RF6 pins. The on-chip voltage reference (Section 21.0 “Comparator Voltage Reference Module”) can also be an input to the comparators. REGISTER 20-1: The CMCON register, shown as Register 20-1, controls the comparator input and output multiplexers.
PIC18F6520/8520/6620/8620/6720/8720 20.1 Comparator Configuration There are eight modes of operation for the comparators. The CMCON register is used to select these modes. Figure 20-1 shows the eight possible modes. The TRISF register controls the data direction of the comparator pins for each mode.
PIC18F6520/8520/6620/8620/6720/8720 20.2 20.3.2 Comparator Operation INTERNAL REFERENCE SIGNAL A single comparator is shown in Figure 20-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 20-3: COMPARATOR OUTPUT BLOCK DIAGRAM Port pins MULTIPLEX + CxINV To RF1 or RF2 pin Bus Data Q Read CMCON Set CMIF bit D EN Q From Other Comparator D EN CL Read CMCON Reset 20.6 Comparator Interrupts The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred.
PIC18F6520/8520/6620/8620/6720/8720 20.7 Comparator Operation During Sleep 20.9 When a comparator is active and the device is placed in Sleep mode, the comparator remains active and the interrupt is functional, if enabled. This interrupt will wake-up the device from Sleep mode, when enabled. While the comparator is powered up, higher Sleep currents than shown in the power-down current specification will occur.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 20-1: Name REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 5 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 0000 0000 TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 INTCON Bit 3 Bit 2 Bit 1 Bit 0 Value on all other Resets Bit 6 CMCON Bit 4 Value on POR Bit 7 GIE/ GIEH PEIE/ GIEL PIR2 — CMIF — — BCLIF LVDIF TMR3IF CCP2IF -0-- 0000 -0-- 0000
PIC18F6520/8520/6620/8620/6720/8720 21.0 COMPARATOR VOLTAGE REFERENCE MODULE 21.1 Configuring the Comparator Voltage Reference The comparator voltage reference is a 16-tap resistor ladder network that provides a selectable voltage reference. The resistor ladder is segmented to provide two ranges of CVREF values and has a power-down function to conserve power when the reference is not being used. The CVRCON register controls the operation of the reference as shown in Register 21-1.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 21-1: VOLTAGE REFERENCE BLOCK DIAGRAM VDD VREF+ CVRSS = 0 16 Stages CVRSS = 1 CVREN 8R R R R R CVRR 8R CVRSS = 0 CVRSS = 1 CVREF 16-1 Analog Mux VREFCVR3 (From CVRCON<3:0>) CVR0 Note: R is defined in Section 26.0 “Electrical Characteristics”. 21.2 Voltage Reference Accuracy/Error 21.4 Effects of a Reset The full range of voltage reference cannot be realized due to the construction of the module.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 21-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE R(1) CVREF Module RF5 + – CVREF Output Voltage Reference Output Impedance Note 1: TABLE 21-1: Name R is dependent upon the Comparator Voltage Reference Configuration bits CVRCON<3:0> and CVRCON<5>.
PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 232 2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720 22.0 LOW-VOLTAGE DETECT In many applications, the ability to determine if the device voltage (VDD) is below a specified voltage level is a desirable feature. A window of operation for the application can be created, where the application software can do “housekeeping tasks” before the device voltage exits the valid operating range. This can be done using the Low-Voltage Detect module.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 22-2: LOW-VOLTAGE DETECT (LVD) BLOCK DIAGRAM LVDIN LVD3:LVD0 LVDCON Register 16 to 1 MUX VDD Internally Generated Reference Voltage (Parameter #D423) LVDEN The LVD module has an additional feature that allows the user to supply the trip voltage to the module from an external source. This mode is enabled when bits LVDL3:LVDL0 are set to ‘1111’.
PIC18F6520/8520/6620/8620/6720/8720 22.1 Control Register The Low-Voltage Detect Control register controls the operation of the Low-Voltage Detect circuitry.
PIC18F6520/8520/6620/8620/6720/8720 22.2 Operation The following steps are needed to set up the LVD module: Depending on the power source for the device voltage, the voltage normally decreases relatively slowly. This means that the LVD module does not need to be constantly operating. To decrease the current requirements, the LVD circuitry only needs to be enabled for short periods, where the voltage is checked. After doing the check, the LVD module may be disabled. 1. 2. 3.
PIC18F6520/8520/6620/8620/6720/8720 22.2.1 REFERENCE VOLTAGE SET POINT The internal reference voltage of the LVD module, specified in electrical specification parameter #D423, may be used by other internal circuitry (the Programmable Brown-out Reset). If these circuits are disabled (lower current consumption), the reference voltage circuit requires a time to become stable before a low-voltage condition can be reliably detected. This time is invariant of system clock speed.
PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 238 2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720 23.0 SPECIAL FEATURES OF THE CPU There are several features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 23-1: CONFIGURATION BITS AND DEVICE IDS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/ Unprogrammed Value 300001h CONFIG1H — — OSCSEN — — FOSC2 FOSC1 FOSC0 --1- -111 300002h CONFIG2L — — — — BORV1 BORV0 BODEN PWRTEN ---- 1111 300003h CONFIG2H — — — — WDTPS2 WDTPS1 WDTPS0 WDTEN ---- 1111 WAIT — — — — — PM1 PM0 1--- --11 300004h(1) CONFIG3L — — — — — r(3) CCP2MX ---- --11 — — — — LV
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 23-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — — — BORV1 BORV0 BOREN PWRTEN bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3-2 BORV1:BORV0: Brown-out Reset Voltage bits 11 = VBOR set to 2.5V 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 23-4: CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h)(1) R/P-1 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1 WAIT — — — — — PM1 PM0 bit 7 bit 0 bit 7 WAIT: External Bus Data Wait Enable bit 1 = Wait selections unavailable for table reads and table writes 0 = Wait selections for table reads and table writes are determined by the WAIT1:WAIT0 bits (MEMCOM<5:4>) bit 6-2 Unimplemented: Read as ‘0’ bit 1-0 PM1:PM0: Processor Mode Select bits 11
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 23-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 U-0 U-0 U-0 U-0 R/P-1 U-0 R/P-1 DEBUG — — — — LVP — STVREN bit 7 bit 0 bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger disabled. RB6 and RB7 configured as general purpose I/O pins. 0 = Background debugger enabled. RB6 and RB7 are dedicated to In-Circuit Debug.
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 23-7: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 CP7(1) CP6(1) CP5(1) CP4(1) CP3 CP2 CP1 CP0 bit 7 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 CP7: Code Protection bit(1) 1 = Block 7 (01C000-01FFFFh) not code-protected 0 = Block 7 (01C000-01FFFFh) code-protected CP6: Code Protection bit(1) 1 = Block 6 (018000-01BFFFh) not code-protected 0 = Block 6 (018000-01BFF
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 23-8: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h) R/C-1 CPD bit 7 bit 7 bit 6 bit 5-0 R/C-1 CPB U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 0 CPD: Data EEPROM Code Protection bit 1 = Data EEPROM not code-protected 0 = Data EEPROM code-protected CPB: Boot Block Code Protection bit For PIC18FX520 devices: 1 = Boot Block (000000-0007FFh) not code-protected 0 = Boot Block (000000-0007FFh) code-protected For PIC18FX620 and PIC18FX720 devices
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 23-9: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 WRT7(1) WRT6(1) WRT5(1) WRT4(1) WRT3 WRT2 WRT1 WRT0 bit 7 bit 0 bit 7 WR7: Write Protection bit(1) 1 = Block 7 (01C000-01FFFFh) not write-protected 0 = Block 7 (01C000-01FFFFh) write-protected bit 6 WR6: Write Protection bit(1) 1 = Block 6 (018000-01BFFFh) not write-protected 0 = Block 6 (018000-01BFFFh) write-protected bit 5
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 23-10: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh) R/P-1 R/P-1 R-1 U-0 U-0 U-0 U-0 U-0 WRTD WRTB WRTC(1) — — — — — bit 7 bit 0 bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM not write-protected 0 = Data EEPROM write-protected bit 6 WRTB: Boot Block Write Protection bit For PIC18FX520 devices: 1 = Boot Block (000000-0007FFh) not write-protected 0 = Boot Block (000000-0007FFh) write-protected For PIC18FX620 and
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 23-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 EBTR7(1) EBTR6(1) EBTR5(1) EBTR4(1) EBTR3 EBTR2 EBTR1 EBTR0 bit 7 bit 0 bit 7 EBTR7: Table Read Protection bit(1) 1 = Block 3 (01C000-01FFFFh) not protected from table reads executed in other blocks 0 = Block 3 (01C000-01FFFFh) protected from table reads executed in other blocks bit 6 EBTR6: Table Read Protection bit(1) 1 = Blo
PIC18F6520/8520/6620/8620/6720/8720 REGISTER 23-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh) U-0 R/P-1 U-0 U-0 U-0 U-0 U-0 U-0 — EBTRB — — — — — — bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 EBTRB: Boot Block Table Read Protection bit For PIC18FX520 devices: 1 = Boot Block (000000-0007FFh) not protected from table reads executed in other blocks 0 = Boot Block (000000-0007FFh) protected from table reads executed in other blocks For PIC18FX620 and PIC18FX720 d
PIC18F6520/8520/6620/8620/6720/8720 23.2 Watchdog Timer (WDT) The Watchdog Timer is a free running, on-chip RC oscillator, which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKI pin. That means that the WDT will run, even if the clock on the OSC1/CLKI and OSC2/CLKO/RA6 pins of the device has been stopped, for example, by execution of a SLEEP instruction.
PIC18F6520/8520/6620/8620/6720/8720 23.2.2 WDT POSTSCALER The WDT has a postscaler that can extend the WDT Reset period. The postscaler is selected at the time of the device programming by the value written to the CONFIG2H Configuration register. FIGURE 23-1: WATCHDOG TIMER BLOCK DIAGRAM WDT Timer Postscaler 8 WDTPS2:WDTPS0 8-to-1 MUX WDTEN Configuration bit SWDTEN bit WDT Time-out Note: TABLE 23-2: Name CONFIG2H RCON WDTCON WDPS2:WDPS0 are bits in register CONFIG2H.
PIC18F6520/8520/6620/8620/6720/8720 23.3 Power-down Mode (Sleep) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared, but keeps running, the PD bit (RCON<3>) is cleared, the TO (RCON<4>) bit is set and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low or high-impedance).
PIC18F6520/8520/6620/8620/6720/8720 WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2) FIGURE 23-2: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKO(4) INT pin INTF flag (INTCON<1>) Interrupt Latency(3) GIEH bit (INTCON<7>) Processor in Sleep INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 23.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 23-3: CODE-PROTECTED PROGRAM MEMORY FOR PIC18FX520 DEVICES Address Range 32 Kbytes Block Code Protection Controlled By: Boot Block 000000h 0007FFh CPB, WRTB, EBTRB Block 0 000800h 001FFFh CP0, WRT0, EBTR0 002000h Block 1 CP1, WRT1, EBTR1 003FFFh 004000h Block 2 CP2, WRT2, EBTR2 005FFFh 006000h Block 3 CP3, WRT3, EBTR3 007FFFh 008000h Unimplemented Read ‘0’s 1FFFFFh FIGURE 23-4: CODE-PROTECTED PROGRAM MEMORY FOR PIC18FX620/X720 DEVICES MEMORY SIZE
PIC18F6520/8520/6620/8620/6720/8720 23.4.1 PROGRAM MEMORY CODE PROTECTION The user memory may be read to, or written from, any location using the table read and table write instructions. The device ID may be read with table reads. The configuration registers may be read and written with the table read and table write instructions. side of that block is not allowed to read and will result in reading ‘0’s.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 23-6: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h 0001FFh 000200h TBLPTR = 000FFFh WRTB, EBTRB = 11 WRT0, EBTR0 = 10 003FFFh 004000h PC = 004FFEh TBLRD * WRT1, EBTR1 = 11 007FFFh 008000h WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: All table reads from external blocks to Block n are disabled whenever EBTRn = 0. TABLAT register returns a value of ‘0’.
PIC18F6520/8520/6620/8620/6720/8720 23.4.2 DATA EEPROM CODE PROTECTION The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits external writes to data EEPROM. The CPU can continue to read and write data EEPROM, regardless of the protection bit settings. 23.4.3 CONFIGURATION REGISTER PROTECTION The configuration registers can be write-protected.
PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 258 2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720 24.0 INSTRUCTION SET SUMMARY The PIC18 instruction set adds many enhancements to the previous PIC MCU instruction sets, while maintaining an easy migration from these PIC MCU instruction sets. Most instructions are a single program memory word (16 bits), but there are three instructions that require two program memory locations.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 24-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 24-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 8 7 OPCODE d a Example Instruction 0 f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 0 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destinati
PIC18F6520/8520/6620/8620/6720/8720 TABLE 24-1: PIC18FXXXX INSTRUCTION SET Mnemonic, Operands 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f
PIC18F6520/8520/6620/8620/6720/8720 TABLE 24-1: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes CONTROL OPERATIONS BC BN BNC BNN BNOV BNZ BOV BRA BZ CALL n n n n n n n n n n, s CLRWDT DAW GOTO — — n NOP NOP POP PUSH RCALL RESET RETFIE — — — — n RETLW RETURN SLEEP 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 s Branch if Carry Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Ov
PIC18F6520/8520/6620/8620/6720/8720 TABLE 24-1: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add literal and WREG AND literal with WREG Inclusive OR literal with WREG Move literal (12-bit) 2nd word to FSRx 1st word Move literal to BSR<3:0> Move literal to WREG Multiply literal with WREG Return with literal in WR
PIC18F6520/8520/6620/8620/6720/8720 24.1 Instruction Set ADDLW ADD literal to W Syntax: [ label ] ADDLW Operands: 0 k 255 Operation: (W) + k W Status Affected: N, OV, C, DC, Z Encoding: 0000 Description: 1111 kkkk kkkk The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.
PIC18F6520/8520/6620/8620/6720/8720 ADDWFC ADD W and Carry bit to f ANDLW AND literal with W Syntax: [ label ] ADDWFC Syntax: [ label ] ANDLW Operands: 0 f 255 d [0,1] a [0,1] f [,d [,a] Operation: (W) + (f) + (C) dest Status Affected: N, OV, C, DC, Z Encoding: 0010 Description: 1 Cycles: 1 0 k 255 Operation: (W) .AND. k W Status Affected: N, Z Encoding: ffff ffff Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W.
PIC18F6520/8520/6620/8620/6720/8720 ANDWF AND W with f Syntax: [ label ] ANDWF Operands: 0 f 255 d [0,1] a [0,1] f [,d [,a] Operation: (W) .AND.
PIC18F6520/8520/6620/8620/6720/8720 BCF Bit Clear f Syntax: [ label ] BCF Operands: 0 f 255 0b7 a [0,1] Operation: 0 f Status Affected: None Encoding: 1001 Description: Branch if Negative Syntax: [ label ] BN Operands: -128 n 127 Operation: if Negative bit is ‘1’ (PC) + 2 + 2n PC Status Affected: None Encoding: bbba ffff ffff 1110 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Read register ‘f’ Process Data Write register ‘f’ Example: BCF Before Instructio
PIC18F6520/8520/6620/8620/6720/8720 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: [ label ] BNC Syntax: [ label ] BNN Operands: -128 n 127 Operands: -128 n 127 Operation: if Carry bit is ‘0’ (PC) + 2 + 2n PC Operation: if Negative bit is ‘0’ (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 n 0011 nnnn nnnn Encoding: 1110 n 0111 nnnn nnnn Description: If the Carry bit is ‘0’, then the program will branch.
PIC18F6520/8520/6620/8620/6720/8720 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: [ label ] BNOV Syntax: [ label ] BNZ Operands: -128 n 127 Operands: -128 n 127 Operation: if Overflow bit is ‘0’ (PC) + 2 + 2n PC Operation: if Zero bit is ‘0’ (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 n 0101 nnnn nnnn Encoding: 1110 n 0001 nnnn nnnn Description: If the Overflow bit is ‘0’, then the program will branch.
PIC18F6520/8520/6620/8620/6720/8720 BRA Unconditional Branch BSF Bit Set f Syntax: [ label ] BRA Syntax: [ label ] BSF Operands: -1024 n 1023 Operands: Operation: (PC) + 2 + 2n PC Status Affected: None 0 f 255 0b7 a [0,1] Operation: 1 f Status Affected: None Encoding: Description: 1101 1 Cycles: 2 Q Cycle Activity: Q1 No operation 0nnn nnnn nnnn Add the 2’s complement number ‘2n’ to the PC.
PIC18F6520/8520/6620/8620/6720/8720 BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: [ label ] BTFSC f,b[,a] Syntax: [ label ] BTFSS f,b[,a] Operands: 0 f 255 0b7 a [0,1] Operands: 0 f 255 0b<7 a [0,1] Operation: skip if (f) = 0 Operation: skip if (f) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction
PIC18F6520/8520/6620/8620/6720/8720 BTG Bit Toggle f BOV Branch if Overflow Syntax: [ label ] BTG f,b[,a] Syntax: [ label ] BOV Operands: 0 f 255 0b<7 a [0,1] Operands: -128 n 127 Operation: if Overflow bit is ‘1’ (PC) + 2 + 2n PC Status Affected: None Operation: (f) f Status Affected: None Encoding: 0111 Description: ffff 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Read register ‘f’ Process Data Write register ‘f’ Example: BTG PORTC, = 0111 0101 [0x7
PIC18F6520/8520/6620/8620/6720/8720 BZ Branch if Zero CALL Subroutine Call Syntax: [ label ] BZ Syntax: [ label ] CALL k [,s] Operands: -128 n 127 Operands: Operation: if Zero bit is ‘1’ (PC) + 2 + 2n PC 0 k 1048575 s [0,1] Operation: (PC) + 4 TOS, k PC<20:1>, if s = 1 (W) WS, (STATUS) STATUSS, (BSR) BSRS Status Affected: None Status Affected: n None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is ‘1’, then the program will branch.
PIC18F6520/8520/6620/8620/6720/8720 CLRF Clear f Syntax: [ label ] CLRF Operands: 0 f 255 a [0,1] Operation: 000h f 1Z Status Affected: Z Encoding: Description: 0110 f [,a] 101a ffff ffff CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 000h WDT, 000h WDT postscaler, 1 TO, 1 PD Status Affected: TO, PD Encoding: 0000 0000 0000 0100 Clears the contents of the specified register.
PIC18F6520/8520/6620/8620/6720/8720 COMF Complement f Syntax: [ label ] COMF Operands: 0 f 255 d [0,1] a [0,1] Operation: ( f ) dest Status Affected: N, Z Encoding: 0001 Description: 1 Cycles: 1 Q Cycle Activity: Q1 Syntax: [ label ] CPFSEQ Operands: 0 f 255 a [0,1] Operation: (f) – (W), skip if (f) = (W) (unsigned comparison) Status Affected: None Encoding: 0110 001a f [,a] ffff ffff Description: Compares the contents of data memory location ‘f’ to the conten
PIC18F6520/8520/6620/8620/6720/8720 CPFSGT Compare f with W, skip if f > W CPFSLT Compare f with W, skip if f < W Syntax: [ label ] CPFSGT Syntax: [ label ] CPFSLT Operands: 0 f 255 a [0,1] Operands: 0 f 255 a [0,1] Operation: (f) W), skip if (f) > (W) (unsigned comparison) Operation: (f) –W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: Description: 0110 010a f [,a] ffff ffff Compares the contents of data memory loc
PIC18F6520/8520/6620/8620/6720/8720 DAW Decimal Adjust W Register DECF Decrement f Syntax: [ label ] DAW Syntax: [ label ] DECF f [,d [,a] Operands: None Operands: Operation: If [W<3:0> >9] or [DC = 1] then (W<3:0>) + 6 W<3:0>; else (W<3:0>) W<3:0>; 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest Status Affected: C, DC, N, OV, Z If [W<7:4> >9] or [C = 1] then (W<7:4>) + 6 W<7:4>; else (W<7:4>) W<7:4>; Status Affected: Encoding: 0000 0000 0000 1 Cycles: 1 Q Cycle Ac
PIC18F6520/8520/6620/8620/6720/8720 DECFSZ Decrement f, skip if 0 DCFSNZ Decrement f, skip if not 0 Syntax: [ label ] DECFSZ f [,d [,a]] Syntax: [ label ] DCFSNZ Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest, skip if result = 0 Operation: (f) – 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Encoding: 0100 11da f [,d [,a] ffff ffff Description: The contents o
PIC18F6520/8520/6620/8620/6720/8720 GOTO Unconditional Branch INCF Increment f Syntax: [ label ] Syntax: [ label ] Operands: 0 k 1048575 Operands: Operation: k PC<20:1> Status Affected: None 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description: 1110 1111 GOTO k 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 GOTO allows an unconditional branch anywhere within the entire 2-Mbyte memory range.
PIC18F6520/8520/6620/8620/6720/8720 INCFSZ Increment f, skip if 0 INFSNZ Increment f, skip if not 0 Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest, skip if result = 0 Operation: (f) + 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0011 INCFSZ 11da f [,d [,a] ffff ffff Encoding: 0100 INFSNZ 10da f [,d [,a] ffff ffff Description: The contents
PIC18F6520/8520/6620/8620/6720/8720 IORLW Inclusive OR literal with W IORWF Inclusive OR W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) .OR. (f) dest Status Affected: N, Z IORLW k Operands: 0 k 255 Operation: (W) .OR.
PIC18F6520/8520/6620/8620/6720/8720 LFSR Load FSR MOVF Move f Syntax: [ label ] Syntax: [ label ] Operands: 0f2 0 k 4095 Operands: Operation: k FSRf 0 f 255 d [0,1] a [0,1] Status Affected: None Operation: f dest Status Affected: N, Z Encoding: LFSR f,k 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the File Select Register pointed to by ‘f’.
PIC18F6520/8520/6620/8620/6720/8720 MOVFF Move f to f MOVLB Move literal to low nibble in BSR Syntax: [ label ] Syntax: [ label ] Operands: 0 fs 4095 0 fd 4095 Operands: 0 k 255 Operation: k BSR None MOVFF fs,fd Operation: (fs) fd Status Affected: Status Affected: None Encoding: Encoding: 1st word (source) 2nd word (destin.) 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register ‘fs’ are moved to destination register ‘fd’.
PIC18F6520/8520/6620/8620/6720/8720 MOVLW Move literal to W MOVWF Move W to f Syntax: [ label ] Syntax: [ label ] Operands: 0 k 255 Operands: Operation: kW 0 f 255 a [0,1] Status Affected: None Operation: (W) f Status Affected: None Encoding: 0000 Description: MOVLW k 1110 kkkk The eight-bit literal ‘k’ is loaded into W.
PIC18F6520/8520/6620/8620/6720/8720 MULLW Multiply Literal with W MULWF Multiply W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 a [0,1] Operation: (W) x (f) PRODH:PRODL Status Affected: None MULLW k Operands: 0 k 255 Operation: (W) x k PRODH:PRODL Status Affected: None Encoding: Description: 0000 1 Cycles: 1 Q Cycle Activity: Q1 Example: kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’.
PIC18F6520/8520/6620/8620/6720/8720 NEGF Negate f Syntax: [ label ] Operands: 0 f 255 a [0,1] NEGF Operation: (f)+1f Status Affected: N, OV, C, DC, Z Encoding: 0110 Description: 1 Cycles: 1 Q Cycle Activity: Q1 Syntax: [ label ] NOP Operands: None Operation: No operation Status Affected: None 0000 1111 ffff Description: 1 Cycles: 1 Decode 0000 xxxx 0000 xxxx No operation.
PIC18F6520/8520/6620/8620/6720/8720 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: (TOS) bit bucket Operation: (PC+2) TOS Status Affected: None Status Affected: None Encoding: 0000 Description: 0000 0000 0110 The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.
PIC18F6520/8520/6620/8620/6720/8720 RCALL Relative Call RESET Reset Syntax: [ label ] RCALL Syntax: [ label ] Operands: Operation: -1024 n 1023 Operands: None (PC) + 2 TOS, (PC) + 2 + 2n PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: Description: 1101 nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC+2) is pushed onto the stack.
PIC18F6520/8520/6620/8620/6720/8720 RETFIE Return from Interrupt RETLW Return Literal to W Syntax: [ label ] Syntax: [ label ] RETFIE [s] RETLW k Operands: s [0,1] Operands: 0 k 255 Operation: (TOS) PC, 1 GIE/GIEH or PEIE/GIEL, if s = 1 (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged Operation: k W, (TOS) PC, PCLATU, PCLATH are unchanged Status Affected: None Status Affected: 0000 0000 0000 0001 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4
PIC18F6520/8520/6620/8620/6720/8720 RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] RETURN [s] RLCF f [,d [,a] Operands: s [0,1] Operands: Operation: (TOS) PC, if s = 1 (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged 0 f 255 d [0,1] a [0,1] Operation: (f) dest, (f<7>) C, (C) dest<0> Status Affected: C, N, Z None Encoding: Status Affected: Encoding: 0000 0000 0001 001s Description
PIC18F6520/8520/6620/8620/6720/8720 RLNCF Rotate Left f (no carry) RRCF Rotate Right f through Carry Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) dest, (f<7>) dest<0> Operation: Status Affected: N, Z (f) dest, (f<0>) C, (C) dest<7> Status Affected: C, N, Z Encoding: 0100 Description: RLNCF 01da f [,d [,a] ffff ffff The contents of register ‘f’ are rotated one bit to
PIC18F6520/8520/6620/8620/6720/8720 RRNCF Rotate Right f (no carry) SETF Set f Syntax: [ label ] Syntax: [ label ] SETF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 a [0,1] Operation: (f) dest, (f<0>) dest<7> FFh f Operation: Status Affected: None Status Affected: N, Z Encoding: 0100 Description: RRNCF 00da f [,d [,a] Encoding: ffff ffff The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W.
PIC18F6520/8520/6620/8620/6720/8720 SLEEP Enter SLEEP mode SUBFWB Subtract f from W with borrow Syntax: [ label ] SLEEP Syntax: [ label ] SUBFWB Operands: None Operands: Operation: 00h WDT, 0 WDT postscaler, 1 TO, 0 PD 0 f 255 d [0,1] a [0,1] Operation: (W) – (f) – (C) dest Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0000 Description: Encoding: 0000 0000 0011 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Q3 Q4 No operation Process Data
PIC18F6520/8520/6620/8620/6720/8720 SUBLW Subtract W from literal SUBWF Subtract W from f Syntax: [ label ] SUBLW k Syntax: [ label ] SUBWF Operands: 0 k 255 Operands: Operation: k – (W) W Status Affected: N, OV, C, DC, Z 0 f 255 d [0,1] a [0,1] Operation: (f) – (W) dest Status Affected: N, OV, C, DC, Z Encoding: 0000 1000 kkkk kkkk Description: W is subtracted from the eight-bit literal ‘k’. The result is placed in W.
PIC18F6520/8520/6620/8620/6720/8720 SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: [ label ] SUBWFB Syntax: [ label ] SWAPF f [,d [,a] Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – (W) – (C) dest Operation: Status Affected: N, OV, C, DC, Z (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> Status Affected: None Encoding: Description: 0101 10da f [,d [,a] ffff ffff Subtract W and the Carry flag (borrow) from register ‘f’ (2
PIC18F6520/8520/6620/8620/6720/8720 TBLRD Table Read TBLRD Table Read (Continued) Syntax: [ label ] Example 1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) TABLAT; TBLPTR – No Change; if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) + 1 TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) – 1 TBLPTR; if TBLRD +*, (TBLPTR) + 1 TBLPTR; (Prog Mem (TBLPTR)) TABLAT; TBLRD ( *; *+; *-; +*) Before Instruction Description: 0000 TABLAT TBLPTR MEMORY(0x00A356) =
PIC18F6520/8520/6620/8620/6720/8720 TBLWT Table Write TBLWT Table Write (Continued) Syntax: [ label ] TBLWT ( *; *+; *-; +*) Words: 1 Operands: None Cycles: 2 Operation: if TBLWT*, (TABLAT) Holding Register; TBLPTR – No Change; if TBLWT*+, (TABLAT) Holding Register; (TBLPTR) + 1 TBLPTR; if TBLWT*-, (TABLAT) Holding Register; (TBLPTR) – 1 TBLPTR; if TBLWT+*, (TBLPTR) + 1 TBLPTR; (TABLAT) Holding Register; Q Cycle Activity: Description: 0000 0000 0000 11nn nn=0 * =1 *+ =2 *=3 +*
PIC18F6520/8520/6620/8620/6720/8720 TSTFSZ Test f, skip if 0 XORLW Exclusive OR literal with W Syntax: [ label ] TSTFSZ f [,a] Syntax: [ label ] XORLW k Operands: 0 f 255 a [0,1] Operands: 0 k 255 Operation: (W) .XOR.
PIC18F6520/8520/6620/8620/6720/8720 XORWF Exclusive OR W with f Syntax: [ label ] XORWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 10da f [,d [,a] ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value.
PIC18F6520/8520/6620/8620/6720/8720 25.
PIC18F6520/8520/6620/8620/6720/8720 25.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use.
PIC18F6520/8520/6620/8620/6720/8720 25.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC18F6520/8520/6620/8620/6720/8720 25.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 25.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC18F6520/8520/6620/8620/6720/8720 26.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) .............................
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 26-1: PIC18F6520/8520 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL, EXTENDED) 6.0V 5.5V Voltage 5.0V PIC18FX520 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V FMAX (Extended) FMAX Frequency FMAX = 40 MHz for PIC18F6520/8520 in Microcontroller mode. FMAX (Extended) = 25 MHz for PIC18F6520/8520 in modes other than Microcontroller mode. FIGURE 26-2: PIC18LF6520/8520 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V PIC18LFX520 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 26-3: PIC18F6620/6720/8620/8720 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL, EXTENDED) 6.0V 5.5V Voltage 5.0V PIC18FX620/X720 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V FMAX (Extended) FMAX Frequency FMAX = 25 MHz in Microcontroller mode. FMAX (Extended) = 16 MHz for PIC18F6520/8520 in modes other than Microcontroller mode. FIGURE 26-4: PIC18LF6620/6720/8620/8720 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V 4.5V PIC18LFX620/X720 4.2V 4.0V 3.5V 3.0V 2.
PIC18F6520/8520/6620/8620/6720/8720 26.
PIC18F6520/8520/6620/8620/6720/8720 26.2 DC Characteristics: Power-Down and Supply Current PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended) PIC18LF6520/8520/6620/8620/6720/8720 (Industrial) PIC18LF6520/8520/6620/8620/6720/8720 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C TA +85°C for industrial PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended) Param No.
PIC18F6520/8520/6620/8620/6720/8720 26.2 DC Characteristics: Power-Down and Supply Current PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended) PIC18LF6520/8520/6620/8620/6720/8720 (Industrial) (Continued) PIC18LF6520/8520/6620/8620/6720/8720 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C TA +85°C for industrial PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended) Param No.
PIC18F6520/8520/6620/8620/6720/8720 26.2 DC Characteristics: Power-Down and Supply Current PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended) PIC18LF6520/8520/6620/8620/6720/8720 (Industrial) (Continued) PIC18LF6520/8520/6620/8620/6720/8720 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C TA +85°C for industrial PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended) Param No.
PIC18F6520/8520/6620/8620/6720/8720 26.2 DC Characteristics: Power-Down and Supply Current PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended) PIC18LF6520/8520/6620/8620/6720/8720 (Industrial) (Continued) PIC18LF6520/8520/6620/8620/6720/8720 Standard Operating Conditions (unless otherwise stated) (Industrial) Operating temperature -40°C TA +85°C for industrial PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended) Param No.
PIC18F6520/8520/6620/8620/6720/8720 26.3 DC Characteristics: PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended) PIC18LF6520/8520/6620/8620/6720/8720 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended DC CHARACTERISTICS Param Sym No. VIL Characteristic Min Max Units Conditions VSS 0.15 VDD V VDD < 4.5V — 0.8 V 4.5V VDD 5.5V VSS VSS 0.2 VDD 0.
PIC18F6520/8520/6620/8620/6720/8720 26.3 DC Characteristics: PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended) PIC18LF6520/8520/6620/8620/6720/8720 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended DC CHARACTERISTICS Param Sym No. Min Max Units — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C — 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40C to +125C — 0.6 V IOL = 1.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-1: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated). Param No. Sym Characteristics Min Typ Max Units D300 VIOFF Input Offset Voltage — ± 5.0 ± 10 mV D301 VICM Input Common Mode Voltage 0 — VDD – 1.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 26-5: LOW-VOLTAGE DETECT CHARACTERISTICS VDD (LVDIF can be cleared in software) VLVD (LVDIF set by hardware) LVDIF TABLE 26-3: LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param Symbol No. D420 D423 Characteristic LVD Voltage on VDD Transition high-to-low VBG Min Typ† Max Units LVV = 0001 1.96 2.06 2.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-4: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended DC Characteristics Param No. Sym Characteristic Min Typ† Max Units 13.25 V Conditions Internal Program Memory Programming Specifications (Note 1) VPP Voltage on MCLR/VPP pin 9.
PIC18F6520/8520/6620/8620/6720/8720 26.4 26.4.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 2.
PIC18F6520/8520/6620/8620/6720/8720 26.4.2 TIMING CONDITIONS The temperature and voltages specified in Table 26-5 apply to all timing specifications unless otherwise noted. Figure 26-6 specifies the load conditions for the timing specifications.
PIC18F6520/8520/6620/8620/6720/8720 26.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 26-7: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 26-6: Param No.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-7: Param No. Sym PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V) Characteristic Min Typ† Max Units Conditions — FOSC Oscillator Frequency Range 4 — 10 MHz HS mode — FSYS On-Chip VCO System Frequency 16 — 40 MHz HS mode — trc PLL Start-up Time (Lock Time) — — 2 ms CLK CLKO Stability (Jitter) -2 — +2 % — † Data in “Typ” column is at 5V, 25C, unless otherwise stated.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-8: Param No. CLKO AND I/O TIMING REQUIREMENTS Symbol Characteristic Min Typ Max Units Conditions (Note 1) 10 TOSH2CKL OSC1 to CLKO — 75 200 ns 11 TOSH2CKH OSC1 to CLKO — 75 200 ns (Note 1) 12 TCKR CLKO Rise Time — 35 100 ns (Note 1) 13 TCKF CLKO Fall Time — 35 100 ns (Note 1) 14 TCKL2IOV CLKO to Port Out Valid — — 0.5 TCY + 20 ns (Note 1) 15 TIOV2CKH Port In Valid before CLKO 0.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-9: Param No. CLKO AND I/O TIMING REQUIREMENTS Symbol Characteristics Min Typ Max Units 0.25 TCY – 10 — — ns 5 — — ns 150 TADV2ALL Address Out Valid to ALE (address setup time) 151 TALL2ADL 155 TALL2OEL ALE to OE 10 0.125 TCY — ns 160 TADZ2OEL AD high-Z to OE (bus release to OE) 0 — — ns 161 TOEH2ADD OE to AD Driven 0.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-10: PROGRAM MEMORY WRITE TIMING REQUIREMENTS Param No. Symbol Characteristics Min Typ Max Units 150 TADV2ALL Address Out Valid to ALE (address setup time) 0.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 26-12: BROWN-OUT RESET TIMING BVDD VDD 35 VBGAP = 1.2V VIRVST Enable Internal Reference Voltage Internal Reference Voltage Stable 36 TABLE 26-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param Symbol No.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-12: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol No. Characteristic 40 TT0H T0CKI High Pulse Width No prescaler 41 TT0L T0CKI Low Pulse Width No prescaler 42 TT0P T0CKI Period Min Max Units 0.5 TCY + 20 — ns With prescaler 10 — ns 0.5 TCY + 20 — ns With prescaler No prescaler With prescaler 45 TT1H T13CKI High Time Synchronous, no prescaler 10 — ns TCY + 10 — ns Greater of: 20 ns or TCY + 40 N — ns 0.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-13: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param Symbol No. 50 51 TCCL Characteristic CCPx Input Low Time TCCH No prescaler With prescaler CCPx Input High Time Units 0.5 TCY + 20 — ns 10 — ns PIC18LFXX20 20 — ns 0.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-14: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F8X20) Param No. 62 Symbol TDTV2WRH TWRH2DTI 63 64 TRDL2DTV Characteristic Min Max Units Conditions Data In Valid before WR or CS (setup time) 20 25 — — ns ns Extended Temp. range WR or CS to Data–In Invalid (hold time) PIC18FXX20 20 — ns PIC18LFXX20 35 — ns VDD = 2.0V — — 80 90 ns ns Extended Temp.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param No. Symbol Characteristic 70 TSSL2SCH, SS to SCK or SCK Input TSSL2SCL 71 TSCH 71A TSCL 72 72A Min TCY Max Units Conditions — ns SCK Input High Time (Slave mode) Continuous 1.25 TCY + 30 — ns Single Byte 40 — ns SCK Input Low Time (Slave mode) Continuous 1.25 TCY + 30 — ns Single Byte 40 — ns 100 — ns 1.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param No. 71 Symbol TSCH SCK Input High Time (Slave mode) TSCL SCK Input Low Time (Slave mode) 71A 72 Characteristic 72A Min Continuous 1.25 TCY + 30 — ns Single Byte 40 — ns Continuous 1.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-17: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param No. Symbol Characteristic 70 TSSL2SCH, SS to SCK or SCK Input TSSL2SCL 71 TSCH 71A TSCL 72 72A Min Max Units Conditions TCY — ns SCK Input High Time (Slave mode) Continuous 1.25 TCY + 30 — ns Single Byte 40 — ns SCK Input Low Time (Slave mode) Continuous 1.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-18: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No. Symbol Characteristic 70 TSSL2SCH, SS to SCK or SCK Input TSSL2SCL 71 TSCH 71A TSCL 72 72A Min Max Units Conditions TCY — ns SCK Input High Time (Slave mode) Continuous 1.25 TCY + 30 — ns Single Byte 40 — ns SCK Input Low Time (Slave mode) Continuous 1.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-19: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param No.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-20: I2C BUS DATA REQUIREMENTS (SLAVE MODE) Param No. 100 Symbol THIGH Characteristic Clock High Time 100 kHz mode 400 kHz mode TLOW Clock Low Time TR 103 TF Units 4.0 — s s — — 100 kHz mode 4.7 — s PIC18FXX20 must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s PIC18FXX20 must operate at a minimum of 10 MHz 1.5 TCY — SDA and SCL Rise 100 kHz mode Time 400 kHz mode — 1000 ns 20 + 0.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 26-22: MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS SCL 93 91 90 92 SDA Stop Condition Start Condition Note: Refer to Figure 26-6 for load conditions. TABLE 26-21: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS Param Symbol No.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-22: MASTER SSP I2C BUS DATA REQUIREMENTS Param Symbol No.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 26-24: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX1/CK1 pin 121 121 RC7/RX1/DT1 pin 120 Note: 122 Refer to Figure 26-6 for load conditions. TABLE 26-23: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-25: A/D CONVERTER CHARACTERISTICS: PIC18FXX20 (INDUSTRIAL, EXTENDED) PIC18LFXX20 (INDUSTRIAL) Param Symbol No. Characteristic Min Typ Max Units Conditions A01 NR Resolution — — 10 A03 EIL Integral Linearity Error — — <±1 LSb VREF = VDD = 5.0V A04 EDL Differential Linearity Error — — <±1 LSb VREF = VDD = 5.0V A05 EG Gain Error — — <±1 LSb VREF = VDD = 5.0V A06 EOFF Offset Error — — <±1.5 LSb VREF = VDD = 5.
PIC18F6520/8520/6620/8620/6720/8720 TABLE 26-26: A/D CONVERSION REQUIREMENTS Param Symbol No. 130 TAD Characteristic A/D Clock Period Min Max Units 1.6 20(5) s TOSC based, VREF 3.0V PIC18LFXX20 3.0 (5) s TOSC based, VREF full range PIC18FXX20 2.0 6.0 s A/D RC mode PIC18LFXX20 A/D RC mode PIC18FXX20 20 Conditions 3.0 9.
PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 340 2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720 27.0 Note: DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 27-3: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE) EXTENDED 20 5.5V 18 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 16 5.0V 4.5V 14 4.0V I DD (mA) 12 3.5V 10 8 3.0V 6 4 2.5V 2 2.0V 0 4 6 8 10 12 14 16 18 20 22 24 26 FOSC (MHz) TYPICAL IDD vs.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 27-5: MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE) INDUSTRIAL 20 18 5.5V Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +85°C) Minimum: mean – 3 (-40°C to +85°C) 16 5.0V 14 4.5V 12 IDD (mA) 4.0V 10 3.5V 8 3.0V 6 4 2.5V 2 2.0V 0 4 6 8 10 12 14 16 18 20 22 24 26 FOSC (MHz) MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE) EXTENDED FIGURE 27-6: 20 5.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 27-7: TYPICAL IDD vs. FOSC OVER VDD (XT MODE) 3.0 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 2.5 2.0 IDD (uA) 5.5V 5.0V 1.5 4.5V 4.0V 1.0 3.5V 3.0V 2.5V 0.5 2.0V 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 3.5 4.0 FOSC (MHz) MAXIMUM IDD vs. FOSC OVER VDD (XT MODE) INDUSTRIAL FIGURE 27-8: 3.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 27-9: TYPICAL IDD vs. FOSC OVER VDD (LP MODE) 100 90 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 80 5.5V 70 5.0V 60 IDD (uA) 4.5V 50 4.0V 3.5V 40 3.0V 30 2.5V 2.0V 20 10 0 0 10 20 30 40 50 60 70 80 90 100 90 100 FOSC (kHz) MAXIMUM IDD vs.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 27-11: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE) EXTENDED 300 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 250 5.5V 5.0V 200 4.5V IDD (uA) 4.0V 150 3.5V 3.0V 2.5V 100 2.0V 50 0 0 10 20 30 40 50 60 70 80 90 100 FOSC (kHz) FIGURE 27-12: TYPICAL IDD vs.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 27-13: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) 18 5.5V Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 16 5.0V 14 4.5V 12 IDD (mA) 4.0V 10 3.5V 8 6 3.0V 4 2.5V 2 2.0V 0 4 6 8 10 12 14 16 18 20 22 24 26 FOSC (MHz) FIGURE 27-14: MAXIMUM IPD vs.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 27-15: TYPICAL AND MAXIMUM IPD vs. VDD OVER TEMPERATURE (TIMER1 AS MAIN OSCILLATOR, 32.768 kHz, C1 AND C2 = 47 pF) 1000 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) IPD (uA) 100 Max (-40°C:+125°C) Max (-40°C:+85°C) 10 Typ (25°C) 1 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 27-16: TYPICAL AND MAXIMUM IWDT vs.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 27-17: TYPICAL IDD vs. FOSC OVER VDD (EC MODE) 0.55 0.50 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 0.45 0.40 5.5V 0.35 IDD (mA) 5.0V 0.30 4.5V 0.25 4.0V 0.20 3.5V 0.15 3.0V 0.10 2.5V 0.05 2.0V 0.00 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.18 0.20 FOSC (MHz) MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) FIGURE 27-18: 0.55 0.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 27-19: TYPICAL IDD vs. FOSC OVER VDD (EC MODE) (PIC18F8520 DEVICES ONLY) 30 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 25 5.5V 20 IDD (mA) 5.0V 4.5V 15 4.2V 4.0V 10 3.5V 3.0V 5 2.5V 2.0V 0 4 8 12 16 20 24 28 32 36 40 FOSC (MHz) FIGURE 27-20: MAXIMUM IDD vs.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 27-21: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) EXTENDED (PIC18F8520 DEVICES ONLY) 20 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 18 16 5.5V 14 5.0V IDD (mA) 12 4.5V 10 4.2V 4.0V 8 3.5V 3.0V 6 4 2.5V 2 2.0V 0 4 6 8 10 12 14 16 18 20 22 24 26 FOSC (MHz) FIGURE 27-22: TYPICAL IDD vs.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 27-23: MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE) INDUSTRIAL (PIC18F8520 DEVICES ONLY) 30 27 5.5V Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +85°C) Minimum: mean – 3 (-40°C to +85°C) 24 5.0V 21 4.5V IDD (mA) 18 4.2V 4.0V 15 12 3.5V 9 3.0V 6 3 2.5V 2.0V 0 4 8 12 16 20 24 28 32 36 40 FOSC (MHz) FIGURE 27-24: MAXIMUM IDD vs.
PIC18F6520/8520/6620/8620/6720/8720 FIGURE 27-25: A/D NONLINEARITY vs. VREFH (VDD = VREFH, -40C TO +125C) 4 3.5 Differential or Integral Nonlinearity (LSB) -40°C -40C 3 +25°C 25C 2.5 +85°C 85C 2 1.5 1 0.5 +125°C 125C 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD and VREFH (V) FIGURE 27-26: A/D NONLINEARITY vs. VREFH (VDD = 5V, -40C TO +125C) 3 Differential or Integral Nonlinearilty (LSB) 2.5 2 1.5 Max +125°C) Max (-40°C (-40C toto125C) 1 Typ Typ (+25°C) (25C) 0.5 0 2 2.5 3 3.5 4 4.
PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 354 2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720 28.0 PACKAGING INFORMATION 28.1 Package Marking Information 64-Lead TQFP (10x10x1 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Example PIC18F6620 -I/PT e3 0410017 80-Lead TQFP (12x12x1 mm) Example XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN PIC18F8720 -E/PT e3 0410017 Legend: XX...
PIC18F6520/8520/6620/8620/6720/8720 28.2 Package Details The following sections give the technical details of the packages.
PIC18F6520/8520/6620/8620/6720/8720 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720 /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 E e E1 N b NOTE 1 12 3 α NOTE 2 A c β φ A2 A1 L1 L 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV 0,//,0(7(56 0,1 1 120 0$; /HDG 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $
PIC18F6520/8520/6620/8620/6720/8720 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 360 2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720 APPENDIX A: REVISION HISTORY Revision A (January 2003) Original data sheet for the PIC18FXX20 family which includes PIC18F6520, PIC18F6620, PIC18F6720, PIC18F8520, PIC18F8620 and PIC18F8720 devices. APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1. This data sheet is based on the previous PIC18FXX20 Data Sheet (DS39580).
PIC18F6520/8520/6620/8620/6720/8720 APPENDIX C: CONVERSION CONSIDERATIONS This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC17C756 to a PIC18F8720.
PIC18F6520/8520/6620/8620/6720/8720 APPENDIX E: MIGRATION FROM HIGH-END TO ENHANCED DEVICES A detailed discussion of the migration pathway and differences between the high-end MCU devices (i.e., PIC17CXXX) and the enhanced devices (i.e., PIC18FXXXX) is provided in AN726, “PIC17CXXX to PIC18CXXX Migration”. This Application Note is available as Literature Number DS00726. 2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 364 2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720 INDEX A A/D ................................................................................... 213 A/D Converter Interrupt, Configuring ....................... 217 Acquisition Requirements ........................................ 218 Acquisition Time ....................................................... 218 ADCON0 Register .................................................... 213 ADCON1 Register .................................................... 213 ADCON2 Register ..
PIC18F6520/8520/6620/8620/6720/8720 Watchdog Timer ....................................................... 251 BN .................................................................................... 268 BNC .................................................................................. 269 BNN .................................................................................. 269 BNOV ............................................................................... 270 BNZ ..................................
PIC18F6520/8520/6620/8620/6720/8720 Map for PIC18FX620/X720 Devices .......................... 49 Special Function Registers ........................................ 47 DAW ................................................................................. 278 DC and AC Characteristics Graphs and Tables .................................................. 341 DC Characteristics PIC18FXX20 (Industrial and Extended), PIC18LFXX20 (Industrial) ........................................................
PIC18F6520/8520/6620/8620/6720/8720 LFSR ........................................................................ 283 MOVF ....................................................................... 283 MOVFF .................................................................... 284 MOVLB .................................................................... 284 MOVLW ................................................................... 285 MOVWF ...................................................................
PIC18F6520/8520/6620/8620/6720/8720 Repeated Start Timing ............................. 186 Master Mode Start Condition ........................... 185 Master Mode Transmission ............................. 187 Multi-Master Communication, Bus Collision and Arbitration .................................................... 191 Multi-Master Mode ........................................... 191 Registers .......................................................... 166 Sleep Operation ...............................
PIC18F6520/8520/6620/8620/6720/8720 RH1/A17 .................................................................... 19 RH2/A18 .................................................................... 19 RH3/A19 .................................................................... 19 RH4/AN12 .................................................................. 19 RH5/AN13 .................................................................. 19 RH6/AN14 ..................................................................
PIC18F6520/8520/6620/8620/6720/8720 Q Q Clock ............................................................................ 154 R RAM. See Data Memory RC Oscillator ...................................................................... 22 RCALL ............................................................................. 289 RCON Registers .............................................................. 101 RCSTA Register SPEN Bit ..................................................................
PIC18F6520/8520/6620/8620/6720/8720 ister .................................................................... 31 SUBFWB .......................................................................... 294 SUBLW ............................................................................ 295 SUBWF ............................................................................ 295 SUBWFB .......................................................................... 296 SWAPF ..............................................
PIC18F6520/8520/6620/8620/6720/8720 with PLL) ............................................................ 27 Transition Between Timer1 and OSC1 (HS, XT, LP) . 26 Transition Between Timer1 and OSC1 (RC, EC) ....... 27 Transition from OSC1 to Timer1 Oscillator ................ 26 USART Asynchronous Reception ............................ 207 USART Asynchronous Transmission ....................... 205 USART Asynchronous Transmission (Back to Back) .... 205 USART Synchronous Receive ( Master/Slave) .......
PIC18F6520/8520/6620/8620/6720/8720 DS39609C-page 374 2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC18F6520/8520/6620/8620/6720/8720 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC18F6520/8520/6620/8620/6720/8720 PIC18F6520/8520/6620/8620/6720/8720 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device Device X Temperature Range /XX XXX Package Pattern PIC18F6520/8520/6620/8620/6720/8720(1), PIC18F6520/8520/6620/8620/6720/8720T(2); VDD range 4.2V to 5.5V PIC18LF6520/8520/6620/8620/6720/8720(1), Examples: a) b) c) PIC18LF6620-I/PT 301 = Industrial temp.
PIC18F6520/8520/6620/8620/6720/8720 NOTES: DS39609C-page 378 2003-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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