Datasheet

PIC18F6390/6490/8390/8490
DS39629C-page 76 © 2007 Microchip Technology Inc.
TABLE 5-2: PIC18F6390/6490/8390/8490 REGISTER FILE SUMMARY
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on page:
TOSU
— — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 59, 66
TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 59, 66
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 59, 66
STKPTR STKFUL STKUNF
— Return Stack Pointer 00-0 0000 59, 67
PCLATU
— — — Holding Register for PC<20:16> ---0 0000 59, 66
PCLATH Holding Register for PC<15:8> 0000 0000 59, 66
PCL PC Low Byte (PC<7:0>) 0000 0000 59, 66
TBLPTRU
— — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 59, 88
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 59, 88
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 59, 88
TABLAT Program Memory Table Latch 0000 0000 59, 88
PRODH Product Register High Byte xxxx xxxx 59, 91
PRODL Product Register Low Byte xxxx xxxx 59, 91
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 59, 95
INTCON2 RBPU
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 59, 96
INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 59, 97
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 59, 82
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 59, 83
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 59, 83
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 59, 83
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register),
value of FSR0 offset by W
N/A 59, 83
FSR0H
— — — — Indirect Data Memory Address Pointer 0 High Byte ---- xxxx 59, 82
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 59, 82
WREG Working Register xxxx xxxx 59
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 59, 82
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 59, 83
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 59, 83
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 59, 83
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register),
value of FSR1 offset by W
N/A 59, 83
FSR1H
— — — — Indirect Data Memory Address Pointer 1 High Byte ---- xxxx 60, 82
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 60, 82
BSR
— — — — Bank Select Register ---- 0000 60, 71
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 60, 82
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 60, 83
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 60, 83
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 60, 83
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register),
value of FSR2 offset by W
N/A 60, 83
FSR2H
— — — — Indirect Data Memory Address Pointer 2 High Byte ---- xxxx 60, 82
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 60, 82
STATUS
— — —NOVZDCC---x xxxx 60, 80
Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
2: These registers and/or bits are not implemented on 64-pin devices; read as ‘0’.
3: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
4: The RG5 bit is only available when Master Clear is disabled (MCLRE Configuration bit = 0); otherwise, RG5 reads as ‘0’. This bit is
read-only.
5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
6: These registers are implemented but unused in 64-pin devices and may be used as general-purpose data RAM if required.