Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 80 (12x12) 8-Bit 40 MHz I/O number 66

PIC18F6390/6490/8390/8490

5.3.4 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and peripheral modules for controlling

the desired operation of the device. These registers are

implemented as static RAM. SFRs start at the top of

data memory (FFFh) and extend downward to occupy

three-quarters of Bank 15 (from F40h to FFFh). A list of

these registers is given in Table 5-1 and Table 5-2.

The SFRs can be classified into two sets: those

associated with the “core” device functionality (ALU,

Resets and interrupts) and those related to the

peripheral functions. The Reset and Interrupt registers

are described in their respective chapters, while the

ALU’s STATUS register is described later in this

section. Registers related to the operation of the

peripheral features are described in the chapter for that

peripheral.

The SFRs are typically distributed among the

peripherals whose functions they control. Unused SFR

locations are unimplemented and read as ‘0’s.

TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F6390/6490/8390/8490 DEVICES

Address Name Address Name Address Name Address Name

FFFh TOSU FDFh INDF2

(1)

FBFh CCPR1H F9Fh IPR1

FFEh TOSH FDEh POSTINC2

(1)

FBEh CCPR1L F9Eh PIR1

FFDh TOSL FDDh POSTDEC2

(1)

FBDh CCP1CON F9Dh PIE1

FFCh STKPTR FDCh PREINC2

(1)

FBCh CCPR2H F9Ch MEMCON

(3)

FFBh PCLATU FDBh PLUSW2

(1)

FBBh CCPR2L F9Bh OSCTUNE

FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah TRISJ

(3)

FF9h PCL FD9h FSR2L FB9h —

(2)

F99h TRISH

(3)

FF8h TBLPTRU FD8h STATUS FB8h —

(2)

F98h TRISG

FF7h TBLPTRH FD7h TMR0H FB7h

—

(2)

F97h TRISF

FF6h TBLPTRL FD6h TMR0L FB6h

—

(2)

F96h TRISE

FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD

FF4h PRODH FD4h

—

(2)

FB4h CMCON F94h TRISC

FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB

FF2h INTCON FD2h HLVDCON FB2h TMR3L F92h TRISA

FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h LATJ

(3)

FF0h INTCON3 FD0h RCON FB0h —

(2)

F90h LATH

(3)

FEFh INDF0

(1)

FCFh TMR1H FAFh SPBRG1 F8Fh LATG

FEEh POSTINC0

(1)

FCEh TMR1L FAEh RCREG1 F8Eh LATF

FEDh POSTDEC0

(1)

FCDh T1CON FADh TXREG1 F8Dh LATE

FECh PREINC0

(1)

FCCh TMR2 FACh TXSTA1 F8Ch LATD

FEBh PLUSW0

(1)

FCBh PR2 FABh RCSTA1 F8Bh LATC

FEAh FSR0H FCAh T2CON FAAh

—

(2)

F8Ah LATB

FE9h FSR0L FC9h SSPBUF FA9h

—

(2)

F89h LATA

FE8h WREG FC8h SSPADD FA8h

—

(2)

F88h PORTJ

(3)

FE7h INDF1

(1)

FC7h SSPSTAT FA7h —

(2)

F87h PORTH

(3)

FE6h POSTINC1

(1)

FC6h SSPCON1 FA6h —

(2)

F86h PORTG

FE5h POSTDEC1

(1)

FC5h SSPCON2 FA5h IPR3 F85h PORTF

FE4h PREINC1

(1)

FC4h ADRESH FA4h PIR3 F84h PORTE

FE3h PLUSW1

(1)

FC3h ADRESL FA3h PIE3 F83h PORTD

FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC

FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB

FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA

Note 1: This is not a physical register.

2: Unimplemented registers are read as ‘0’.

3: This register is not available on 64-pin devices.

4: This register is implemented but unused on 64-pin devices.