Datasheet
PIC18F6390/6490/8390/8490
DS39629C-page 62 © 2007 Microchip Technology Inc.
TRISJ 6X90 8X90 1111 1111 1111 1111 uuuu uuuu
TRISH 6X90 8X90 1111 1111 1111 1111 uuuu uuuu
TRISG 6X90 8X90 ---1 1111 ---1 1111 ---u uuuu
TRISF 6X90 8X90 1111 1111 1111 1111 uuuu uuuu
TRISE 6X90 8X90 1111 ---- 1111 ---- uuuu ----
TRISD 6X90 8X90 1111 1111 1111 1111 uuuu uuuu
TRISC 6X90 8X90 1111 1111 1111 1111 uuuu uuuu
TRISB 6X90 8X90 1111 1111 1111 1111 uuuu uuuu
TRISA
(5)
6X90 8X90 1111 1111
(5)
1111 1111
(5)
uuuu uuuu
(5)
LATJ 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LATH
6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LATG 6X90 8X90 ---x xxxx ---u uuuu ---u uuuu
LATF 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LATE 6X90 8X90 xxxx ---- uuuu ---- uuuu ----
LATD 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LATC 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LATB 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
LATA
(5)
6X90 8X90 xxxx xxxx
(5)
uuuu uuuu
(5)
uuuu uuuu
(5)
PORTJ 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
PORTH 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
PORTG 6X90 8X90 --xx xxxx --uu uuuu --uu uuuu
PORTF 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
PORTE 6X90 8X90 xxxx ---- uuuu ---- uuuu ----
PORTD 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
PORTC 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
PORTB 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
PORTA
(5)
6X90 8X90 xx0x 0000
(5)
uu0u 0000
(5)
uuuu uuuu
(5)
SPBRGH1 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
BAUDCON1 6X90 8X90 01-0 0-00 01-0 0-00 uu-u u-uu
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable
Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: These registers are cleared on POR and unchanged on BOR.