Datasheet
PIC18F6390/6490/8390/8490
DS39629C-page 60 © 2007 Microchip Technology Inc.
FSR1H 6X90 8X90 ---- xxxx ---- uuuu ---- uuuu
FSR1L 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
BSR 6X90 8X90 ---- 0000 ---- 0000 ---- uuuu
INDF2 6X90 8X90 N/A N/A N/A
POSTINC2 6X90 8X90 N/A N/A N/A
POSTDEC2 6X90 8X90 N/A N/A N/A
PREINC2 6X90 8X90 N/A N/A N/A
PLUSW2 6X90 8X90 N/A N/A N/A
FSR2H 6X90 8X90 ---- xxxx ---- uuuu ---- uuuu
FSR2L 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
STATUS 6X90 8X90 ---x xxxx ---u uuuu ---u uuuu
TMR0H 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
TMR0L 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
T0CON 6X90 8X90 1111 1111 1111 1111 uuuu uuuu
OSCCON 6X90 8X90 0100 q000 0100 00q0 uuuu uuqu
HLVDCON 6X90 8X90 0-00 0101 0-00 0101 u-uu uuuu
WDTCON 6X90 8X90 ---- ---0 ---- ---0 ---- ---u
RCON
(4)
6X90 8X90 0q-1 11q0 0q-q qquu uq-u qquu
TMR1H 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1L 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 6X90 8X90 0000 0000 u0uu uuuu uuuu uuuu
TMR2 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
PR2 6X90 8X90 1111 1111 1111 1111 1111 1111
T2CON 6X90 8X90 -000 0000 -000 0000 -uuu uuuu
SSPBUF 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu
SSPADD 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
SSPCON1 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
SSPCON2 6X90 8X90 0000 0000 0000 0000 uuuu uuuu
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable
Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: These registers are cleared on POR and unchanged on BOR.