Datasheet

© 2007 Microchip Technology Inc. DS39629C-page 383
PIC18F6390/6490/8390/8490
FIGURE 26-19: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 26-21: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 26-20: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 26-22: USART SYNCHRONOUS RECEIVE REQUIREMENTS
121
121
120
122
RC6/TX1/CK1
RC7/RX1/DT1
pin
pin
Note: Refer to Figure 26-4 for load conditions.
Param
No.
Symbol Characteristic Min Max Units Conditions
120 T
CKH2DTV SYNC XMIT (MASTER and SLAVE)
Clock High to Data Out Valid PIC18FXXXX — 40 ns
PIC18LFXXXX — 100 ns VDD = 2.0V
121 T
CKRF Clock Out Rise Time and Fall Time
(Master mode)
PIC18FXXXX — 20 ns
PIC18LFXXXX — 50 ns VDD = 2.0V
122 TDTRF Data Out Rise Time and Fall Time PIC18FXXXX — 20 ns
PIC18LFXXXX — 50 ns V
DD = 2.0V
125
126
RC6/TX1/CK1
RC7/RX1/DT1
pin
pin
Note: Refer to Figure 26-4 for load conditions.
Param.
No.
Symbol Characteristic Min Max Units Conditions
125 T
DTV2CKL SYNC RCV (MASTER and SLAVE)
Data Hold before CKx ↓ (DTx hold time) 10 — ns
126 T
CKL2DTL Data Hold after CKx ↓ (DTx hold time) 15 — ns