Datasheet

PIC18F6390/6490/8390/8490
DS39629C-page 376 © 2007 Microchip Technology Inc.
FIGURE 26-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
TABLE 26-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
81
71 72
74
75, 76
78
80
MSb
79
73
MSb In
bit 6 - - - - - - 1
LSb In
bit 6 - - - - 1
LSb
Note: Refer to Figure 26-4 for load conditions.
Param.
No.
Symbol Characteristic Min Max Units Conditions
71 TSCH SCK Input High Time
(Slave mode)
Continuous 1.25 TCY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 T
SCL SCK Input Low Time
(Slave mode)
Continuous 1.25 TCY + 30 — ns
72A Single Byte 40 — ns (Note 1)
73 T
DIV2SCH,
T
DIV2SCL
Setup Time of SDI Data Input to SCK Edge 100 — ns
73A T
B2B Last Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2
1.5 TCY + 40 — ns (Note 2)
74 T
SCH2DIL,
T
SCL2DIL
Hold Time of SDI Data Input to SCK Edge 100 — ns
75 T
DOR SDO Data Output Rise Time PIC18FXXXX — 25 ns
PIC18LFXXXX — 45 ns VDD = 2.0V
76 TDOF SDO Data Output Fall Time — 25 ns
78 T
SCR SCK Output Rise Time
(Master mode)
PIC18FXXXX — 25 ns
PIC18LFXXXX — 45 ns V
DD = 2.0V
79 T
SCF SCK Output Fall Time (Master mode) — 25 ns
80 T
SCH2DOV,
T
SCL2DOV
SDO Data Output Valid after
SCK Edge
PIC18FXXXX — 50 ns
PIC18LFXXXX — 100 ns V
DD = 2.0V
81 TDOV2SCH,
T
DOV2SCL
SDO Data Output Setup to SCK Edge T
CY —ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.