Datasheet

PIC18F6390/6490/8390/8490
DS39629C-page 372 © 2007 Microchip Technology Inc.
FIGURE 26-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
FIGURE 26-8: BROWN-OUT RESET TIMING
TABLE 26-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol Characteristic Min Typ Max Units Conditions
30 T
MCLMCLR Pulse Width (low) 2 — — μs
31 T
WDT Watchdog Timer Time-out Period
(No postscaler)
3.4 4.0 4.6 ms
32 T
OST Oscillator Start-up Timer Period 1024 TOSC — 1024 TOSC —TOSC = OSC1 period
33 T
PWRT Power-up Timer Period 55.5 65.5 75 ms
34 T
IOZ I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
—2—μs
35 T
BOR Brown-out Reset Pulse Width 200 — — μsVDD ≤ BVDD (see D005)
36 T
IRVST Time for Internal Reference
Voltage to become Stable
—2050 μs
37 T
LVD Low-Voltage Detect Pulse Width 200 — — μsVDD ≤ VLVD
38 TCSD CPU Start-up Time — 10 — μs
39 T
IOBST Time for INTRC Block to Stabilize — 1 — ms
VDD
MCLR
Internal
POR
PWRT
Time-out
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O pins
34
Note: Refer to Figure 26-4 for load conditions.
VDD
BVDD
35
VBGAP = 1.2V
V
IRVST
Enable Internal
Internal Reference
36
Reference Voltage
Voltage Stable