Datasheet

PIC18F6390/6490/8390/8490
DS39629C-page 196 © 2007 Microchip Technology Inc.
TABLE 15-4: REGISTERS ASSOCIATED WITH I
2
C™ OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values on
Page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 59
PIR1
— ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 61
PIE1 — ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 61
IPR1
— ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 61
TRISC PORTC Data Direction Register 62
SSPBUF MSSP Receive Buffer/Transmit Register 60
SSPADD MSSP Address Register in I
2
C Slave Mode. MSSP Baud Rate Reload Register in I
2
C Slave Mode. 60
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 60
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 60
SSPSTAT SMP CKE
D/A P S R/W UA BF 60
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.