Datasheet

PIC18F6390/6490/8390/8490
DS39629C-page 126 © 2007 Microchip Technology Inc.
TABLE 9-14: PORTG FUNCTIONS
TABLE 9-15: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Pin Name Function
TRIS
Setting
I/O Buffer Description
RG0/SEG30 RG0 0 O DIG LATG<0> data output; disabled when LCD segment enabled.
1 I ST PORTG<0> data input.
SEG30 x O ANA Segment 30 analog output for LCD.
RG1/TX2/CK2/
SEG29
RG1 0 O DIG LATG<1> data output; disabled when LCD segment enabled.
1 I ST PORTG<1> data input.
TX2 1 O DIG Synchronous serial data output (AUSART module); takes priority over
port data.
CK2 1 O DIG Synchronous serial data input (AUSART module). User must configure
as an input.
1 I ST Synchronous serial clock input (AUSART module).
SEG29 x O ANA Segment 29 analog output for LCD.
RG2/RX2/DT2/
SEG28
RG2 0 O DIG LATG<2> data output; disabled when LCD segment enabled.
1 I ST PORTG<2> data input.
RX2 1 I ST Asynchronous serial receive data input (AUSART module).
DT2 1 O DIG Synchronous serial data output (AUSART module); takes priority over
port data.
1 I ST Synchronous serial data input (AUSART module). User must configure
as an input.
SEG28 x O ANA Segment 28 analog output for LCD.
RG3/SEG27 RG3 0 O DIG LATG<3> data output; disabled when LCD segment enabled.
1 I ST PORTG<3> data input.
SEG27 0 O ANA Segment 27 analog output for LCD.
RG4/SEG26 RG4 0 O DIG LATG<4> data output; disabled when LCD segment enabled.
1 I ST PORTG<4> data input.
SEG26 x O ANA Segment 26 analog output for LCD.
MCLR
/VPP/RG5 MCLR —
(1)
I ST External Master Clear input; enabled when MCLRE Configuration bit is set.
V
PP —
(1)
I ANA High-voltage detection; used for ICSP™ mode entry detection. Always
available, regardless of pin mode.
RG5 —
(1)
I ST PORTG<5> data input; enabled when MCLRE Configuration bit is clear.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: RG5 does not have a corresponding TRISG bit.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset Values
on Page
PORTG
— —RG5
(1)
Read PORTG pin/Write PORTG Data Latch 62
LATG
— — — LATG Data Output Register 62
TRISG
— — — PORTG Data Direction Register 62
LCDSE3 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 64
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG.
Note 1: RG5 is available as an input only when MCLR is disabled.