Datasheet

© 2007 Microchip Technology Inc. DS39629C-page 121
PIC18F6390/6490/8390/8490
TABLE 9-10: PORTE FUNCTIONS
TABLE 9-11: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Pad Name Function
TRIS
Setting
I/O Buffer Description
RE4/COM1 RE4 0 O DIG LATE<4> data output; disabled when LCD common enabled.
1 I ST PORTE<4> data input.
COM1 x O ANA Common 1 analog output for LCD.
RE5/COM2 RE5 0 O DIG LATE<5> data output; disabled when LCD common enabled.
1 I ST PORTE<5> data input.
COM2 x O ANA Common 2 analog output for LCD.
RE6/COM3 RE6 0 O DIG LATE<6> data output; disabled when LCD segment enabled.
1 I ST PORTE<6> data input.
COM3 x O ANA Common 3 analog output for LCD.
RE7/CCP2/
SEG31
RE7 0 O DIG LATE<7> data output; disabled when LCD segment enabled.
1 I ST PORTE<7> data input.
CCP2
(1)
0 O DIG CCP2 compare output and CCP2 PWM output; takes priority over port data.
1 I ST CCP2 capture input.
SEG31 x O ANA Segment 31 analog output for LCD.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Alternate assignment for CCP2 when the CCP2MX Configuration bit = 0.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page
PORTE RE7 RE6 RE5 RE4
— — — —62
LATE LATE Data Output Register — — — —62
TRISE PORTE Data Direction Register — — — —62
LCDCON
LCDEN SLPEN WERR — CS1 CS0 LMUX1 LMUX0 64
LCDSE3 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 64
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.