Datasheet

PIC18F6390/6490/8390/8490
DS39629C-page 120 © 2007 Microchip Technology Inc.
9.5 PORTE, TRISE and
LATE Registers
PORTE is a 4-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISE bit (= 0)
will make the corresponding PORTE pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
All pins on PORTE are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Pins RE6:RE4 are multiplexed with three of the LCD
common drives. I/O port functions are only available on
those PORTE pins, depending on which commons are
active. The configuration is determined by the
LMUX1:LMUX0 control bits (LCDCON<1:0>). The
availability is summarized in Table 9-9.
RE7 is also multiplexed with LCD segment drive
(SEG31) controlled by the LCDSE3<7> bit. I/O port
function is only available when the segment is disabled.
RE7 also can be configured as the alternate peripheral
pin for the CCP2 module. This is done by clearing the
CCP2MX Configuration bit.
TABLE 9-9: PORTE PINS AVAILABLE IN
DIFFERENT LCD DRIVE
CONFIGURATIONS
EXAMPLE 9-5: INITIALIZING PORTE
Note: On a Power-on Reset, these pins are
configured as digital inputs.
Note: The pins corresponding to RE2:RE0 of
other PIC18F parts have the function of
LCDBIAS3:LCDBIAS1 and the pin
corresponding to RE3 of other PIC18F
parts has the function of COM0. These four
pins cannot be used as digital I/O.
LCDCON
<1:0>
Active LCD
Commons
PORTE Available
for I/O
00 COM0 RE6, RE5, RE4
01 COM0, COM1 RE6, RE5
10 COM0, COM1
and COM2
RE6
11 All (COM0
through COM3)
None
CLRF PORTE ; Initialize PORTE by
; clearing output
; data latches
CLRF LATE ; Alternate method
; to clear output
; data latches
MOVLW 30h ; Value used to
; initialize data
; direction
MOVWF TRISE ; Set RE<5:4> as inputs
; RE<7:6> as outputs