Datasheet

PIC18F6390/6490/8390/8490
DS39629C-page 116 © 2007 Microchip Technology Inc.
TABLE 9-5: PORTC FUNCTIONS
Pin Name Function
TRIS
Setting
I/O Buffer Description
RC0/T1OSO/
T13CKI/
RC0 0 O DIG LATC<0> data output; disabled when Timer1 oscillator is used.
1 I ST PORTC<0> data input; disabled when Timer1 oscillator is used.
T1OSO x O ANA Timer1 oscillator output.
T13CKI x I ST Timer1/Timer3 clock input.
RC1/T1OSI/
CCP2
RC1 0 O DIG LATC<1> data output; disabled when Timer1 oscillator is used.
1 I ST PORTC<1> data input; disabled when Timer1 oscillator is used.
T1OSI x I ANA Timer1 oscillator input.
CCP2
(1)
0 O DIG CCP2 compare output or PWM output; takes priority over digital I/O data.
1 I ST CCP2 capture input.
RC2/CCP1/
SEG13
RC2 0 O DIG LATC<2> data output; disabled when LCD segment enabled.
1 I ST PORTC<2> data input.
CCP1 0 O DIG CCP1 compare output or PWM output; takes priority over digital I/O data.
1 I ST CCP1 capture input.
SEG13 x O ANA Segment 13 analog output for LCD.
RC3/SCK/SCL RC3 0 O DIG LATC<3> data output.
1 I ST PORTC<3> data input.
SCK 0 O DIG SPI clock output (MSSP module); takes priority over port data.
1 I ST SPI clock input (MSSP module).
SCL 0 ODIGI
2
C™ clock output (MSSP module); takes priority over port data.
1 ISTI
2
C clock input (MSSP module); input type depends on module setting.
RC4/SDI/SDA RC4 0 O DIG LATC<4> data output.
1 I ST PORTC<4> data input.
SDI 1 I ST SPI data input (MSSP module).
SDA 1 ODIGI
2
C data output (MSSP module); takes priority over port data.
1 ISTI
2
C data input (MSSP module); input type depends on module setting.
RC5/SDO/
SEG12
RC5 0 O DIG LATC<5> data output; disabled when LCD segment enabled.
1 I ST PORTC<5> data input.
SDO 0 O DIG SPI data output (MSSP module); takes priority over port data.
SEG12 x O ANA Segment 12 analog output for LCD.
RC6/TX1/CK1 RC6 0 O DIG LATC<6> data output.
1 I ST PORTC<6> data input.
TX1 1 O DIG Synchronous serial data output (EUSART module); takes priority over
port data.
CK1 1 O DIG Synchronous serial data input (EUSART module). User must configure
as an input.
1 I ST Synchronous serial clock input (EUSART module).
RC7/RX1/DT1 RC7 0 O DIG LATC<7> data output.
1 I ST PORTC<7> data input.
RX1 1 I ST Asynchronous serial receive data input (EUSART module).
DT1 1 O DIG Synchronous serial data output (EUSART module); takes priority over
port data.
1 I ST Synchronous serial data input (EUSART module). User must configure
as an input.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Default assignment for CCP2 (CCP2MX Configuration bit = 1).