Datasheet

© 2007 Microchip Technology Inc. DS39629C-page 109
PIC18F6390/6490/8390/8490
9.0 I/O PORTS
Depending on the device selected and features
enabled, there are up to nine ports available. Some
pins of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
• TRIS register (data direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (output latch)
The Data Latch (LAT register) is useful for
read-modify-write operations on the value that the I/O
pins are driving.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 9-1.
FIGURE 9-1: GENERIC I/O PORT
OPERATION
9.1 PORTA, TRISA and
LATA Registers
PORTA is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch.
The Data Latch register (LATA) is also memory mapped.
Read-modify-write operations on the LATA register read
and write the latched output value for PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input and the LCD segment drive to become the
RA4/T0CKI/SEG14 pin. Pins RA6 and RA7 are
multiplexed with the main oscillator pins; they are
enabled as oscillator or I/O pins by the selection of the
main oscillator in the Configuration register (see
Section 23.1 “Configuration Bits” for details). When
they are not used as port pins, RA6 and RA7 and their
associated TRIS and LAT bits are read as ‘0’.
The other PORTA pins are multiplexed with analog
inputs and the analog V
REF+ and VREF- inputs. The
operation of pins RA3:RA0 and RA5 as A/D converter
inputs is selected by clearing or setting the control bits
in the ADCON1 register (A/D Control Register 1).
The RA4/T0CKI/SEG14 pin is a Schmitt Trigger input
and an open-drain output. All other PORTA pins have
TTL input levels and full CMOS output drivers.
The TRISA register controls the direction of the PORTA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
RA5:RA2 are also multiplexed with LCD segment
drives controlled by bits in the LCDSE1 and
LCDSE2 registers. I/O port functions are only
available when the segments are disabled.
EXAMPLE 9-1: INITIALIZING PORTA
Data
Bus
WR LAT
WR TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Input
Buffer
I/O pin
(1)
QD
CK
QD
CK
EN
QD
EN
RD LAT
or PORT
Note 1: I/O pins have diode protection to V
DD and VSS.
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
CLRF LATA ; Alternate method
; to clear output
; data latches
MOVLW 07h ; Configure A/D
MOVWF ADCON1 ; for digital inputs
MOVWF 07h ; Configure comparators
MOVWF CMCON ; for digital input
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<5:4> as outputs