Datasheet

PIC18F6390/6490/8390/8490
DS39629C-page 106 © 2007 Microchip Technology Inc.
REGISTER 8-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
U-0 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0
— LCDIP RC2IP TX2IP — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 LCDIP: LCD Interrupt Priority bit (valid when Type-B waveform with Non-Static mode is selected)
1 =High priority
0 = Low priority
bit 5 RC2IP: AUSART Receive Interrupt Priority bit
1 =High priority
0 = Low priority
bit 4 TX2IP: AUSART Transmit Interrupt Priority bit
1 =High priority
0 = Low priority
bit 3-0 Unimplemented: Read as ‘0’