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PIC18F6390/6490/8390/8490

Data Sheet

64/80-Pin Flash Microcontrollers

with LCD Driver and nanoWatt Technology

Summary of content (414 pages)

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PIC18F6390/6490/8390/8490 Data Sheet 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology © 2007 Microchip Technology Inc.
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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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PIC18F6390/6490/8390/8490 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology LCD Driver Module Features: Peripheral Highlights: • Direct Driving of LCD Panel • Up to 48 Segments: Software Selectable • Programmable LCD Timing module: - Multiple LCD timing sources available - Up to 4 commons: Static, 1/2, 1/3 or 1/4 multiplex - Static, 1/2 or 1/3 bias configuration • Can drive LCD Panel while in Sleep mode • • • • • Power-Managed Modes: • • Run: CPU On, Peripherals On Idle: CPU Off
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PIC18F6390/6490/8390/8490 Pin Diagrams RD7/SEG7 RD6/SEG6 RD5/SEG5 RD4/SEG4 RD3/SEG3 RD2/SEG2 RD1/SEG1 VSS VDD RE7/CCP2(1)/SEG31 RD0/SEG0 RE6/COM3 RE5/COM2 RE4/COM1 COM0 LCDBIAS3 64-Pin TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 LCDBIAS2 LCDBIAS1 RG0/SEG30 RG1/TX2/CK2/SEG29 RF7/SS/SEG25 RF6/AN11/SEG24 RF5/AN10/CVREF/SEG23 RF4/AN9/SEG22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RF3/AN8/SEG21 RF2/AN7/C1OUT/SEG20 15 16 RG2/RX2/DT2/SEG28 RG3/SEG27 MCLR/VPP/RG5 RG4/SEG26 VSS VDD 48 47 46
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PIC18F6390/6490/8390/8490 Pin Diagrams (Continued) RJ1/SEG33 RJ0/SEG32 RD7/SEG7 RD6/SEG6 RD5/SEG5 RD4/SEG4 RD3/SEG3 RD2/SEG2 RD1/SEG1 VDD VSS RD0/SEG0 RE7/CCP2(1)/SEG31 RE6/COM3 RE5/COM2 RE4/COM1 COM0 LCDBIAS3 RH0/SEG47 RH1/SEG46 80-Pin TQFP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RH2/SEG45 RH3/SEG44 LCDBIAS2 LCDBIAS1 RG0/SEG30 RG1/TX2/CK2/SEG29 RG2/RX2/DT2/SEG28 RG3/SEG27 MCLR/VPP/RG5 RG4/SEG26 VSS VDD RF7/SS/SEG25 RF6/AN11/SEG24 RF5/AN10/CVREF/SEG23 RF4/AN9/SEG22
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PIC18F6390/6490/8390/8490 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Oscillator Configurations ............................................................................................................................................................ 31 3.0 Power-Managed Modes .............................................................
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PIC18F6390/6490/8390/8490 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
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PIC18F6390/6490/8390/8490 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC18F6390 • PIC18F8390 • PIC18F6490 • PIC18F8490 This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price.
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PIC18F6390/6490/8390/8490 1.2 Other Special Features • Memory Endurance: The Flash cells for program memory are rated to last for approximately a thousand erase/write cycles. Data retention without refresh is conservatively estimated to be greater than 100 years. • Extended Instruction Set: The PIC18F6390/6490/8390/8490 family introduces an optional extension to the PIC18 instruction set, which adds 8 new instructions and an Indexed Addressing mode.
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PIC18F6390/6490/8390/8490 TABLE 1-1: DEVICE FEATURES Features PIC18F6390 PIC18F6490 PIC18F8390 PIC18F8490 DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz 8K 16K 8K 16K Program Memory (Instructions) 4096 8192 4096 8192 Data Memory (Bytes) 768 768 768 768 22 22 22 22 Operating Frequency Program Memory (Bytes) Interrupt Sources I/O Ports Number of Pixels the LCD Driver can Drive Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E, F, G F, G F, G, H,
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PIC18F6390/6490/8390/8490 FIGURE 1-1: PIC18F6X90 (64-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> Data Latch 8 8 inc/dec logic PORTA Data Memory (3.
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PIC18F6390/6490/8390/8490 FIGURE 1-2: PIC18F8X90 (80-PIN) BLOCK DIAGRAM PORTA Data Bus<8> Table Pointer<21> Data Latch 8 8 inc/dec logic Data Memory (3.
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PIC18F6390/6490/8390/8490 TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS Pin Name MCLR/VPP/RG5 MCLR Pin Number TQFP 7 VPP RG5 OSC1/CLKI/RA7 OSC1 I ST P I ST 39 I CLKI I RA7 OSC2/CLKO/RA6 OSC2 Pin Buffer Type Type I/O Description Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. Oscillator crystal or external clock input.
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PIC18F6390/6490/8390/8490 TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 24 RA1/AN1 RA1 AN1 23 RA2/AN2/VREF-/SEG16 RA2 AN2 VREFSEG16 22 RA3/AN3/VREF+/SEG17 RA3 AN3 VREF+ SEG17 21 RA4/T0CKI/SEG14 RA4 T0CKI SEG14 28 RA5/AN4/HLVDIN/SEG15 RA5 AN4 HLVDIN SEG15 27 I/O I TTL Analog Digital I/O. Analog input 0. I/O I TTL Analog Digital I/O. Analog input 1.
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PIC18F6390/6490/8390/8490 TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
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PIC18F6390/6490/8390/8490 TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 30 RC1/T1OSI/CCP2 RC1 T1OSI CCP2(1) 29 RC2/CCP1/SEG13 RC2 CCP1 SEG13 33 RC3/SCK/SCL RC3 SCK SCL 34 RC4/SDI/SDA RC4 SDI SDA 35 RC5/SDO/SEG12 RC5 SDO SEG12 36 RC6/TX1/CK1 RC6 TX1 CK1 31 RC7/RX1/DT1 RC7 RX1 DT1 32 I/O O I ST — ST I/O I I/O ST CMOS ST Digital I/O.
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PIC18F6390/6490/8390/8490 TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTD is a bidirectional I/O port. RD0/SEG0 RD0 SEG0 58 RD1/SEG1 RD1 SEG1 55 RD2/SEG2 RD2 SEG2 54 RD3/SEG3 RD3 SEG3 53 RD4/SEG4 RD4 SEG4 52 RD5/SEG5 RD5 SEG5 51 RD6/SEG6 RD6 SEG6 50 RD7/SEG7 RD7 SEG7 49 I/O O ST Analog Digital I/O. SEG0 output for LCD. I/O O ST Analog Digital I/O. SEG1 output for LCD. I/O O ST Analog Digital I/O.
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PIC18F6390/6490/8390/8490 TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTE is a bidirectional I/O port. LCDBIAS1 LCDBIAS1 2 LCDBIAS2 LCDBIAS2 1 LCDBIAS3 LCDBIAS3 64 COM0 COM0 63 RE4/COM1 RE4 COM1 62 RE5/COM2 RE5 COM2 61 RE6/COM3 RE6 COM3 60 RE7/CCP2/SEG31 RE7 CCP2(2) SEG31 59 I Analog BIAS1 input for LCD. I Analog BIAS2 input for LCD. I Analog BIAS3 input for LCD. O Analog COM0 output for LCD.
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PIC18F6390/6490/8390/8490 TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTF is a bidirectional I/O port.
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PIC18F6390/6490/8390/8490 TABLE 1-2: PIC18F6X90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTG is a bidirectional I/O port. RG0/SEG30 RG0 SEG30 3 RG1/TX2/CK2/SEG29 RG1 TX2 CK2 SEG29 4 RG2/RX2/DT2/SEG28 RG2 RX2 DT2 SEG28 5 RG3/SEG27 RG3 SEG27 6 RG4/SEG26 RG4 SEG26 8 I/O O ST Analog Digital I/O. SEG30 output for LCD. I/O O I/O O ST — ST Analog Digital I/O. AUSART2 asynchronous transmit. AUSART2 synchronous clock (see related RX2/DT2).
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PIC18F6390/6490/8390/8490 TABLE 1-3: PIC18F8X90 PINOUT I/O DESCRIPTIONS Pin Name MCLR/VPP/RG5 MCLR Pin Number TQFP 9 VPP RG5 OSC1/CLKI/RA7 OSC1 Pin Buffer Type Type I ST P I ST 49 I CLKI I RA7 I/O OSC2/CLKO/RA6 OSC2 Description Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. Oscillator crystal or external clock input.
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PIC18F6390/6490/8390/8490 TABLE 1-3: PIC18F8X90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 30 RA1/AN1 RA1 AN1 29 RA2/AN2/VREF-/SEG16 RA2 AN2 VREFSEG16 28 RA3/AN3/VREF+/SEG17 RA3 AN3 VREF+ SEG17 27 RA4/T0CKI/SEG14 RA4 T0CKI SEG14 34 RA5/AN4/HLVDIN/SEG15 RA5 AN4 HLVDIN SEG15 33 I/O I TTL Analog Digital I/O. Analog input 0. I/O I TTL Analog Digital I/O. Analog input 1.
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PIC18F6390/6490/8390/8490 TABLE 1-3: PIC18F8X90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
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PIC18F6390/6490/8390/8490 TABLE 1-3: PIC18F8X90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 36 RC1/T1OSI/CCP2 RC1 T1OSI CCP2(1) 35 RC2/CCP1/SEG13 RC2 CCP1 SEG13 43 RC3/SCK/SCL RC3 SCK SCL 44 RC4/SDI/SDA RC4 SDI SDA 45 RC5/SDO/SEG12 RC5 SDO SEG12 46 RC6/TX1/CK1 RC6 TX1 CK1 37 RC7/RX1/DT1 RC7 RX1 DT1 38 I/O O I ST — ST Digital I/O. Timer1 oscillator output.
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PIC18F6390/6490/8390/8490 TABLE 1-3: PIC18F8X90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTD is a bidirectional I/O port. RD0/SEG0 RD0 SEG0 72 RD1/SEG1 RD1 SEG1 69 RD2/SEG2 RD2 SEG2 68 RD3/SEG3 RD3 SEG3 67 RD4/SEG4 RD4 SEG4 66 RD5/SEG5 RD5 SEG5 65 RD6/SEG6 RD6 SEG6 64 RD7/SEG7 RD7 SEG7 63 I/O O ST Analog Digital I/O. SEG0 output for LCD. I/O O ST Analog Digital I/O. SEG1 output for LCD. I/O O ST Analog Digital I/O.
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PIC18F6390/6490/8390/8490 TABLE 1-3: PIC18F8X90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTE is a bidirectional I/O port. LCDBIAS1 LCDBIAS1 4 LCDBIAS2 LCDBIAS2 3 LCDBIAS3 LCDBIAS3 78 COM0 COM0 77 RE4/COM1 RE4 COM1 76 RE5/COM2 RE5 COM2 75 RE6/COM3 RE6 COM3 74 RE7/CCP2/SEG31 RE7 CCP2(2) SEG31 73 I Analog BIAS1 input for LCD. I Analog BIAS2 input for LCD. I Analog BIAS3 input for LCD. O Analog COM0 output for LCD.
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PIC18F6390/6490/8390/8490 TABLE 1-3: PIC18F8X90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTF is a bidirectional I/O port.
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PIC18F6390/6490/8390/8490 TABLE 1-3: PIC18F8X90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTG is a bidirectional I/O port. RG0/SEG30 RG0 SEG30 5 RG1/TX2/CK2/SEG29 RG1 TX2 CK2 SEG29 6 RG2/RX2/DT2/SEG28 RG2 RX2 DT2 SEG28 7 RG3/SEG27 RG3 SEG27 8 RG4/SEG26 RG4 SEG26 10 RG5 I/O O ST Analog Digital I/O. SEG30 output for LCD. I/O O I/O O ST — ST Analog Digital I/O. AUSART2 asynchronous transmit.
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PIC18F6390/6490/8390/8490 TABLE 1-3: PIC18F8X90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTH is a bidirectional I/O port. RH0/SEG47 RH0 SEG47 79 RH1/SEG46 RH1 SEG46 80 RH2/SEG45 RH2 SEG45 1 RH3/SEG44 RH3 SEG44 2 RH4/SEG40 RH4 SEG40 22 RH5/SEG41 RH5 SEG41 21 RH6/SEG42 RH6 SEG42 20 RH7/SEG43 RH7 SEG43 19 I/O O ST Analog Digital I/O. SEG47 output for LCD. I/O O ST Analog Digital I/O. SEG46 output for LCD.
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PIC18F6390/6490/8390/8490 TABLE 1-3: PIC18F8X90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTJ is a bidirectional I/O port. RJ0/SEG32 RJ0 SEG32 62 RJ1/SEG33 RJ1 SEG33 61 RJ2/SEG34 RJ2 SEG34 60 RJ3/SEG35 RJ3 SEG35 59 RJ4/SEG39 RJ4 SEG39 39 RJ5/SEG38 RJ5 SEG38 40 RJ6/SEG37 RJ6 SEG37 41 RJ7/SEG36 RJ7 SEG36 42 I/O O ST Analog Digital I/O. SEG32 output for LCD. I/O O ST Analog Digital I/O. SEG33 output for LCD.
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PIC18F6390/6490/8390/8490 2.0 OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types PIC18F6390/6490/8390/8490 devices can be operated in ten different oscillator modes. The user can program the Configuration bits, FOSC3:FOSC0, in Configuration Register 1H to select one of these ten modes: 1. 2. 3. 4. LP XT HS HSPLL Low-Power Crystal Crystal/Resonator High-Speed Crystal/Resonator High-Speed Crystal/Resonator with PLL Enabled 5. RC External Resistor/Capacitor with FOSC/4 Output on RA6 6.
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PIC18F6390/6490/8390/8490 TABLE 2-2: Osc Type LP XT HS CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Freq Typical Capacitor Values Tested: C1 C2 32 kHz 33 pF 33 pF 200 kHz 15 pF 15 pF 1 MHz 33 pF 33 pF 4 MHz 27 pF 27 pF 4 MHz 27 pF 27 pF 8 MHz 22 pF 22 pF 20 MHz 15 pF 15 pF Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized.
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PIC18F6390/6490/8390/8490 2.4 RC Oscillator 2.5 For timing insensitive applications, the “RC” and “RCIO” device options offer additional cost savings.
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PIC18F6390/6490/8390/8490 2.6 Internal Oscillator Block The PIC18F6390/6490/8390/8490 devices include an internal oscillator block, which generates two different clock signals; either can be used as the microcontroller’s clock source. This may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC) is an 8 MHz clock source, which can be used to directly drive the device clock.
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PIC18F6390/6490/8390/8490 2.6.5.1 Compensating with the AUSART An adjustment may be required when the AUSART begins to generate framing errors or receives data with errors while in Asynchronous mode. Framing errors indicate that the device clock frequency is too high. To adjust for this, decrement the value in OSTUNE to reduce the clock frequency. On the other hand, errors in data may suggest that the clock speed is too low. To compensate, increment OSTUNE to increase the clock frequency. 2.6.5.
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PIC18F6390/6490/8390/8490 2.7 Clock Sources and Oscillator Switching Like previous PIC18 devices, the PIC18F6390/6490/8390/8490 family includes a feature that allows the device clock source to be switched from the main oscillator to an alternate low-frequency clock source. PIC18F6390/6490/8390/8490 devices offer two alternate clock sources. When an alternate clock source is enabled, the various power-managed operating modes are available.
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PIC18F6390/6490/8390/8490 2.7.1 OSCILLATOR CONTROL REGISTER The OSCCON register (Register 2-2) controls several aspects of the device clock’s operation, both in full-power operation and in power-managed modes. The System Clock Select bits, SCS1:SCS0, select the clock source. The available clock sources are the primary clock (defined by the FOSC:FOSC0 Configuration bits), the secondary clock (Timer1 oscillator) and the internal oscillator block.
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PIC18F6390/6490/8390/8490 REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF2:IRCF0: Inte
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PIC18F6390/6490/8390/8490 2.8 Effects of Power-Managed Modes on the Various Clock Sources When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin, if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the device clock.
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PIC18F6390/6490/8390/8490 3.0 POWER-MANAGED MODES 3.1.1 The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: PIC18F6390/6490/8390/8490 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices).
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PIC18F6390/6490/8390/8490 3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Three bits indicate the current clock source and its status. They are: • OSTS (OSCCON<3>) • IOFS (OSCCON<2>) • T1RUN (T1CON<6>) In general, only one of these bits will be set while in a given power-managed mode.
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PIC18F6390/6490/8390/8490 FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 1 T1OSI 2 3 n-1 Q3 Q4 Q1 Q2 Q3 n Clock Transition OSC1 CPU Clock Peripheral Clock Program Counter PC FIGURE 3-2: PC + 2 PC + 4 TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI OSC1 TOST(1) TPLL(1) PLL Clock Output 1 CPU Clock 2 n-1 Clock Transition n Peripheral Clock Program Counter SCS1:SCS0 bits Changed PC + 2 PC PC + 4 O
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PIC18F6390/6490/8390/8490 3.2.3 RC_RUN MODE If the IRCF bits and the INTSRC bit are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. The INTRC source provides the device clocks. In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer and the primary clock is shut down.
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PIC18F6390/6490/8390/8490 3.3 Sleep Mode 3.4 The power-managed Sleep mode in the PIC18F6390/6490/8390/8490 devices is identical to the legacy Sleep mode offered in all other PIC devices. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (see Figure 3-5). All clock source status bits are cleared. Entering the Sleep mode from any other mode does not require a clock switch.
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PIC18F6390/6490/8390/8490 3.4.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing-sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “warm up” or transition from another oscillator. When a wake event occurs, the CPU is clocked from the primary clock source.
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PIC18F6390/6490/8390/8490 3.4.2 SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered from SEC_RUN by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then set SCS1:SCS0 to ‘01’ and execute SLEEP. When the clock source is switched to the Timer1 oscillator, the primary oscillator is shut down, the OSTS bit is cleared and the T1RUN bit is set.
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PIC18F6390/6490/8390/8490 3.5 Exiting Idle and Sleep Modes An exit from Sleep mode or any of the Idle modes is triggered by an interrupt, a Reset or a WDT time-out. This section discusses the triggers that cause exits from power-managed modes. The clocking subsystem actions are discussed in each of the power-managed modes (see Section 3.2 “Run Modes” through Section 3.4 “Idle Modes”). 3.5.
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PIC18F6390/6490/8390/8490 TABLE 3-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES) Clock Source before Wake-up Clock Source after Wake-up Exit Delay LP, XT, HS Primary Device Clock (PRI_IDLE mode) HSPLL EC, RC, INTRC(1) OSTS TCSD(2) INTOSC(3) T1OSC or INTRC(1) HSPLL TOST + trc(4) EC, RC, INTRC(1) TCSD(2) — TIOBST(5) TOST(5) TOST + trc(4) TCSD(2) IOFS OSTS None IOFS (3) HSPLL EC, RC, INTRC(1) INTOSC Note 1: 2: 3: 4: 5: IOFS TOST(4) INTOSC None (Sl
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PIC18F6390/6490/8390/8490 4.0 RESET 4.1 The PIC18F6390/6490/8390/8490 devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during power-managed modes Watchdog Timer (WDT) Reset (during execution) Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset This section discusses Resets generated by MCLR, POR and BOR and covers the operation of the various start-up timers.
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PIC18F6390/6490/8390/8490 REGISTER 4-1: R/W-0 IPEN RCON: RESET CONTROL REGISTER R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0 R/W-0 SBOREN — RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR So
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PIC18F6390/6490/8390/8490 4.2 Master Clear (MCLR) The MCLR pin provides a method for triggering a hard external Reset of the device. A Reset is generated by holding the pin low. PIC18 Extended MCU devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. FIGURE 4-2: In PIC18F6390/6490/8390/8490 devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section 9.
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PIC18F6390/6490/8390/8490 4.4 Brown-out Reset (BOR) PIC18F6390/6490/8390/8490 devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV1:BORV0 and BOREN1:BOREN0 Configuration bits. There are a total of four BOR configurations, which are summarized in Table 4-1. The BOR threshold is set by the BORV1:BORV0 bits.
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PIC18F6390/6490/8390/8490 4.5 Device Reset Timers 4.5.3 PIC18F6390/6490/8390/8490 devices incorporate three separate on-chip timers that help regulate the Power-on Reset process. Their main function is to ensure that the device clock is stable before code is executed. These timers are: • Power-up Timer (PWRT) • Oscillator Start-up Timer (OST) • PLL Lock Time-out 4.5.
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PIC18F6390/6490/8390/8490 FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 FIGURE 4-4: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 4-5: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS39629C-page 56 ©
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PIC18F6390/6490/8390/8490 FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 1V 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 4-7: TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT OST TIME-OUT TOST TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL ≈ 2 ms max. First three stages of the PWRT timer. © 2007 Microchip Technology Inc.
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PIC18F6390/6490/8390/8490 4.6 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Table 4-4 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups.
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PIC18F6390/6490/8390/8490 TABLE 4-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt TOSU 6X90 8X90 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 6X90 8X90 0000 0000 0000 0000 uuuu uuuu(3) TOSL 6X90 8X90 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 6X90 8X90 00-0 0000 00-0 0000 uu-u uuuu(3) PCLATU 6X90 8X90 ---0 0000 ---0 0000 ---u uuuu PCLATH 6X90
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PIC18F6390/6490/8390/8490 TABLE 4-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt FSR1H 6X90 8X90 ---- xxxx ---- uuuu ---- uuuu FSR1L 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu BSR 6X90 8X90 ---- 0000 ---- 0000 ---- uuuu INDF2 6X90 8X90 N/A N/A N/A POSTINC2 6X90 8X90 N/A N/A N/A POSTDEC2 6X90 8X90 N/A N/A N/A PREINC2 6
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PIC18F6390/6490/8390/8490 TABLE 4-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt ADRESH 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL 6X90 8X90 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 6X90 8X90 --00 0000 --00 0000 --uu uuuu ADCON1 6X90 8X90 --00 0000 --00 0000 --uu uuuu ADCON2 6X90 8X90 0-00 0000 0-00 0000 u-uu uuuu CCPR1H
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PIC18F6390/6490/8390/8490 TABLE 4-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt TRISJ 6X90 8X90 1111 1111 1111 1111 uuuu uuuu TRISH 6X90 8X90 1111 1111 1111 1111 uuuu uuuu TRISG 6X90 8X90 ---1 1111 ---1 1111 ---u uuuu TRISF 6X90 8X90 1111 1111 1111 1111 uuuu uuuu TRISE 6X90 8X90 1111 ---- 1111 ---- uuuu ---- TRISD 6X90
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PIC18F6390/6490/8390/8490 TABLE 4-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt LCDDATA23 6X90 8X90 xxxx xxxx 0000 0000 uuuu uuuu LCDDATA22 6X90 8X90 xxxx xxxx 0000 0000 uuuu uuuu LCDDATA21 6X90 8X90 xxxx xxxx 0000 0000 uuuu uuuu LCDDATA20 6X90 8X90 xxxx xxxx 0000 0000 uuuu uuuu LCDDATA19 6X90 8X90 xxxx xxxx 0000 0000 uuu
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PIC18F6390/6490/8390/8490 TABLE 4-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt LCDSE5 6X90 8X90 0000 0000 0000 0000(6) uuuu uuuu LCDSE4 6X90 8X90 0000 0000 0000 0000(6) uuuu uuuu (6) uuuu uuuu LCDSE3 6X90 8X90 0000 0000 0000 0000 LCDSE2 6X90 8X90 0000 0000 0000 0000(6) uuuu uuuu 0000(6) uuuu uuuu LCDSE1 6X90 8X90 0000 0
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PIC18F6390/6490/8390/8490 5.0 MEMORY ORGANIZATION There are two types of memory in PIC18 Flash microcontroller devices: • Program Memory • Data RAM As Harvard architecture devices, the data and program memories use separate busses; this allows for concurrent access of the two memory spaces. Additional detailed information on the operation of the Flash program memory is provided in Section 6.0 “Flash Program Memory”. 5.
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PIC18F6390/6490/8390/8490 5.1.1 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU.
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PIC18F6390/6490/8390/8490 5.1.2.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 5-1) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. On Reset, the Stack Pointer value will be zero. The user may read and write the Stack Pointer value.
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PIC18F6390/6490/8390/8490 5.1.2.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause a device Reset.
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PIC18F6390/6490/8390/8490 5.2 PIC18 Instruction Cycle 5.2.1 5.2.2 An “Instruction Cycle” consists of four Q cycles, Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.
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PIC18F6390/6490/8390/8490 5.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read ‘0’ (see Section 5.1.1 “Program Counter”).
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PIC18F6390/6490/8390/8490 5.3 Note: Data Memory Organization The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 5.6 “Data Memory and the Extended Instruction Set” for more information. The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory.
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PIC18F6390/6490/8390/8490 FIGURE 5-5: DATA MEMORY MAP FOR PIC18F6390/6490/8390/8490 DEVICES BSR<3:0> 00h = 0000 = 0001 = 0010 Bank 0 FFh 00h GPR 000h 05Fh 060h 0FFh 100h GPR Bank 1 Bank 2 Access RAM 1FFh 200h FFh 00h The BSR is ignored and the Access Bank is used. The first 128 bytes are general purpose RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15).
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PIC18F6390/6490/8390/8490 FIGURE 5-6: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) 7 0 0 0 0 0 0 0 Bank Select(2) 1 0 000h Data Memory Bank 0 100h Bank 1 200h Bank 2 300h 00h 7 FFh 00h 11 From Opcode(2) 11 11 11 11 1 0 1 1 FFh 00h FFh 00h Bank 3 through Bank 13 E00h Bank 14 F00h FFFh Note 1: 2: 5.3.
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PIC18F6390/6490/8390/8490 5.3.4 SPECIAL FUNCTION REGISTERS The SFRs can be classified into two sets: those associated with the “core” device functionality (ALU, Resets and interrupts) and those related to the peripheral functions. The Reset and Interrupt registers are described in their respective chapters, while the ALU’s STATUS register is described later in this section. Registers related to the operation of the peripheral features are described in the chapter for that peripheral.
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PIC18F6390/6490/8390/8490 TABLE 5-1: Address SPECIAL FUNCTION REGISTER MAP FOR PIC18F6390/6490/8390/8490 DEVICES (CONTINUED) Name F7Fh Address SPBRGH1 F6Fh Name Address SPBRG2 F5Fh F7Eh BAUDCON1 F6Eh RCREG2 F5Eh F7Dh —(2) Address Name LCDSE5 (3) F4Fh —(2) LCDSE4 (3) F4Eh —(2) F6Dh TXREG2 F5Dh LCDSE3 F4Dh —(2) (4) F6Ch TXSTA2 F5Ch LCDSE2 F4Ch —(2) LCDDATA22(4) F6Bh RCSTA2 F5Bh LCDSE1 F4Bh —(2) F7Ch LCDDATA23 F7Bh Name F7Ah LCDDATA21 F6Ah LCDDATA10 F5Ah LCD
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PIC18F6390/6490/8390/8490 TABLE 5-2: File Name TOSU PIC18F6390/6490/8390/8490 REGISTER FILE SUMMARY Bit 7 Bit 6 Bit 5 — — — TOSH Top-of-Stack High Byte (TOS<15:8>) TOSL Top-of-Stack Low Byte (TOS<7:0>) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Top-of-Stack Upper Byte (TOS<20:16>) Value on POR, BOR Details on page: ---0 0000 59, 66 0000 0000 59, 66 0000 0000 59, 66 STKPTR STKFUL STKUNF — Return Stack Pointer 00-0 0000 59, 67 PCLATU — — — Holding Register for PC<20:16> ---0 0000 59,
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PIC18F6390/6490/8390/8490 TABLE 5-2: File Name PIC18F6390/6490/8390/8490 REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: TMR0H Timer0 Register High Byte 0000 0000 60, 132 TMR0L Timer0 Register Low Byte xxxx xxxx 60, 132 60, 131 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 OSCCON T0CON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 38, 60 HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 H
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PIC18F6390/6490/8390/8490 TABLE 5-2: File Name PIC18F6390/6490/8390/8490 REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: SPBRG1 EUSART1 Baud Rate Generator Register Low Byte 0000 0000 61, 201 RCREG1 EUSART1 Receive Register 0000 0000 61, 208 TXREG1 EUSART1 Transmit Register 0000 0000 61, 206 TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 61, 198 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR R
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PIC18F6390/6490/8390/8490 TABLE 5-2: File Name PIC18F6390/6490/8390/8490 REGISTER FILE SUMMARY (CONTINUED) Bit 7 SPBRGH1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR EUSART1 Baud Rate Generator Register High Byte BAUDCON1 Details on page: 0000 0000 62, 201 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 62, 200 63, 261 LCDDATA23(6) S47C3 S46C3 S45C3 S44C3 S43C3 S42C3 S41C3 S40C3 xxxx xxxx LCDDATA22(6) S39C3 S38C3 S37C3 S36C3 S35C3 S34C3 S33C3 S32C3
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PIC18F6390/6490/8390/8490 5.3.5 STATUS REGISTER The STATUS register, shown in Register 5-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the status is updated according to the instruction performed.
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PIC18F6390/6490/8390/8490 5.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 5.6 “Data Memory and the Extended Instruction Set” for more information. While the program memory can be addressed in only one way – through the program counter – information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed.
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PIC18F6390/6490/8390/8490 5.4.3.1 FSR Registers and the INDF Operand mapped in the SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction’s target.
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PIC18F6390/6490/8390/8490 5.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value.
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PIC18F6390/6490/8390/8490 5.5 Program Memory and the Extended Instruction Set The operation of program memory is unaffected by the use of the extended instruction set. Enabling the extended instruction set adds five additional two-word commands to the existing PIC18 instruction set: ADDFSR, CALLW, MOVSF, MOVSS and SUBFSR. These instructions are executed as described in Section 5.2.4 “Two-Word Instructions”. 5.
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PIC18F6390/6490/8390/8490 FIGURE 5-8: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When a = 0 and f ≥ 60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and FFFh. This is the same as locations F60h to FFFh (Bank 15) of data memory. Locations below 060h are not available in this addressing mode.
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PIC18F6390/6490/8390/8490 5.6.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the lower part of Access RAM (00h to 5Fh) is mapped. Rather than containing just the contents of the bottom part of Bank 0, this mode maps the contents from Bank 0 and a user-defined “window” that can be located anywhere in the data memory space.
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PIC18F6390/6490/8390/8490 6.0 FLASH PROGRAM MEMORY In PIC18F6390/6490/8390/8490 devices, the program memory is implemented as read-only Flash memory. It is readable over the entire VDD range during normal operation. A read from program memory is executed on one byte at a time. 6.1 Table Reads For PIC18 devices, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: table read (TBLRD) and table write (TBLWT).
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PIC18F6390/6490/8390/8490 6.2 Control Registers TABLE 6-1: TABLE POINTER OPERATIONS WITH TBLRD INSTRUCTIONS Example Operation on Table Pointer Two control registers are used in conjunction with the TBLRD instruction: the TABLAT register and the TBLPTR register set. 6.2.1 TABLE LATCH REGISTER (TABLAT) The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.
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PIC18F6390/6490/8390/8490 EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base ; address of the word READ_WORD TBLRD*+ MOVF MOVWF TBLRD*+ MOVF MOVWF TABLE 6-2: Name TBLPTRU ; read into TABLAT and increment ; get data TABLAT, W WORD_EVEN ; read into TABLAT and increment ; get data TABLAT, W WORD_ODD REGISTERS ASSOCIATED WITH READING PROGRAM FLASH MEMORY Bit 7 Bit 6 Bit
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PIC18F6390/6490/8390/8490 7.0 8 x 8 HARDWARE MULTIPLIER 7.1 Introduction EXAMPLE 7-1: MOVF MULWF All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS register. ARG1, W ARG2 EXAMPLE 7-2: Making multiplication a hardware operation allows it to be completed in a single instruction cycle.
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PIC18F6390/6490/8390/8490 Example 7-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 7-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0).
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PIC18F6390/6490/8390/8490 8.0 INTERRUPTS The PIC18F6390/6490/8390/8490 devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The highpriority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress.
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PIC18F6390/6490/8390/8490 FIGURE 8-1: PIC18F6X90/8X90 INTERRUPT LOGIC Wake-up if in Idle or Sleep modes TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP PIR1<6:0> PIE1<6:0> IPR1<6:0> PIR2<7:6, 3:0> PIE2<7:6, 3:0> IPR2<7:6, 3:0> Interrupt to CPU Vector to Location 0008h GIE/GIEH IPEN PIR3<6:4> PIE3<6:4> IPR3<6:4> IPEN PEIE/GIEL IPEN High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<6:0> PIE1<6:0> IPR1<6:0> PIR2<
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PIC18F6390/6490/8390/8490 8.1 INTCON Registers Note: The INTCON registers are readable and writable registers which contain various enable, priority and flag bits. REGISTER 8-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
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PIC18F6390/6490/8390/8490 REGISTER 8-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: Exter
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PIC18F6390/6490/8390/8490 REGISTER 8-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0
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PIC18F6390/6490/8390/8490 8.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). REGISTER 8-4: Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit, GIE (INTCON<7>).
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PIC18F6390/6490/8390/8490 REGISTER 8-5: R/W-0 PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 CMIF — — BCLIF HLVDIF TMR3IF CCP2IF OSCFIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software)
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PIC18F6390/6490/8390/8490 REGISTER 8-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 U-0 R/W-0 R-0 R/W-0 U-0 U-0 U-0 U-0 — LCDIF RC2IF TX2IF — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 LCDIF: LCD Interrupt Flag bit (valid when Type-B waveform with Non-Static mode is selected) 1 = LCD data of all COMs is ou
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PIC18F6390/6490/8390/8490 8.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2, PIE3). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts.
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PIC18F6390/6490/8390/8490 REGISTER 8-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE CMIE — — BCLIE HLVDIE TMR3IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5-4 Unimplement
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PIC18F6390/6490/8390/8490 REGISTER 8-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 R/W-0 R-0 R-0 U-0 U-0 U-0 U-0 — LCDIE RC2IE TX2IE — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 LCDIE: LCD Interrupt Enable bit (valid when Type-B waveform with Non-Static mode is selected) 1 = Enabled 0 = Disabled bit 5 RC2IE
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PIC18F6390/6490/8390/8490 8.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.
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PIC18F6390/6490/8390/8490 REGISTER 8-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP CMIP — — BCLIP HLVDIP TMR3IP CCP2IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Low pri
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PIC18F6390/6490/8390/8490 REGISTER 8-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0 — LCDIP RC2IP TX2IP — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 LCDIP: LCD Interrupt Priority bit (valid when Type-B waveform with Non-Static mode is selected) 1 = High priority 0 = Low pri
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PIC18F6390/6490/8390/8490 8.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the bit that enables interrupt priorities (IPEN).
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PIC18F6390/6490/8390/8490 8.6 INTx Pin Interrupts 8.7 TMR0 Interrupt External interrupts on the RB0/INT0, RB1/INT1, RB2/ INT2 and RB3/INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit INTxIF is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxIE.
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PIC18F6390/6490/8390/8490 9.0 I/O PORTS 9.1 Depending on the device selected and features enabled, there are up to nine ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation.
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PIC18F6390/6490/8390/8490 TABLE 9-1: Pin Name PORTA FUNCTIONS Function TRIS Setting I/O Buffer RA0 0 O DIG 1 I TTL PORTA<0> data input. Reads ‘0’ on POR. AN0 1 I ANA A/D input channel 0. Default configuration on POR. RA1 0 O DIG LATA<1> data output. Not affected by analog pin setting. RA0/AN0 RA1/AN1 RA2/AN2/VREF-/ SEG16 RA3/AN3/VREF+/ SEG17 RA4/T0CKI/ SEG14 LATA<0> data output. Not affected by analog pin setting. 1 I TTL PORTA<1> data input. Reads ‘0’ on POR.
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PIC18F6390/6490/8390/8490 TABLE 9-2: Name PORTA SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 (1) LATA6(1) LATA Data Output Register LATA LATA7 TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Register Reset Values on Page 62 62 62 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 61 LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 64 LCDSE2 SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 6
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PIC18F6390/6490/8390/8490 9.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped.
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PIC18F6390/6490/8390/8490 TABLE 9-3: Pin Name RB0/INT0 RB1/INT1/SEG8 RB2/INT2/SEG9 PORTB FUNCTIONS Function TRIS Setting I/O Buffer RB0 0 O DIG LATB<0> data output. 1 I TTL PORTB<0> data input; programmable weak pull-up. INT0 1 I ST External interrupt 0 input. RB1 0 O DIG LATB<1> data output; disabled when LCD segment enabled. PORTB<1> data input; weak pull-up when RBPU bit is cleared. 1 I TTL INT1 1 I ST SEG8 x O ANA Segment 8 analog output for LCD.
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PIC18F6390/6490/8390/8490 TABLE 9-4: Name PORTB SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 62 LATB LATB Data Output Register 62 TRISB PORTB Data Direction Register 62 INTCON GIE/GIEH PEIE/GIEL TMR0IF INT0IF RBIF 59 INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP TMR0IE INT0IE RBIE INT3IP RBIP 59 INT3IF INT2IF INT1IF 59 SE10 SE9 SE8 64 INTCON2 RBPU INTCON3 INT2IP INT1I
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PIC18F6390/6490/8390/8490 9.3 PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATC) is also memory mapped.
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PIC18F6390/6490/8390/8490 TABLE 9-5: Pin Name PORTC FUNCTIONS Function TRIS Setting I/O Buffer RC0 0 O DIG 1 I ST T1OSO x O ANA T13CKI x I ST Timer1/Timer3 clock input. RC1 0 O DIG LATC<1> data output; disabled when Timer1 oscillator is used. 1 I ST T1OSI x I ANA Timer1 oscillator input. CCP2(1) 0 O DIG CCP2 compare output or PWM output; takes priority over digital I/O data.
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PIC18F6390/6490/8390/8490 TABLE 9-6: Name PORTC SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 62 LATC LATC Data Output Register 62 TRISC PORTC Data Direction Register 62 LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 64 Legend: Shaded cells are not used by PORTC. © 2007 Microchip Technology Inc.
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PIC18F6390/6490/8390/8490 9.4 PORTD, TRISD and LATD Registers PORTD is also multiplexed with LCD segment drives controlled by the LCDSE0 register. I/O port functions are only available when the segments are disabled. PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode).
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PIC18F6390/6490/8390/8490 TABLE 9-8: Name PORTD SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 62 LATD LATD Data Output Register 62 TRISD PORTD Data Direction Register 62 LCDSE0 SE7 SE6 © 2007 Microchip Technology Inc.
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PIC18F6390/6490/8390/8490 9.5 PORTE, TRISE and LATE Registers PORTE is a 4-bit wide, bidirectional port. The corresponding Data Direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATE) is also memory mapped.
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PIC18F6390/6490/8390/8490 TABLE 9-10: Pad Name PORTE FUNCTIONS Function TRIS Setting I/O Buffer RE4 0 O DIG 1 I ST COM1 x O ANA Common 1 analog output for LCD. RE5 0 O DIG LATE<5> data output; disabled when LCD common enabled. 1 I ST COM2 x O ANA Common 2 analog output for LCD. RE6 0 O DIG LATE<6> data output; disabled when LCD segment enabled. 1 I ST PORTE<6> data input. RE4/COM1 RE5/COM2 RE6/COM3 RE7/CCP2/ SEG31 PORTE PORTE<5> data input.
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PIC18F6390/6490/8390/8490 9.6 PORTF, LATF and TRISF Registers PORTF is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISF. Setting a TRISF bit (= 1) will make the corresponding PORTF pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISF bit (= 0) will make the corresponding PORTF pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATF) is also memory mapped.
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PIC18F6390/6490/8390/8490 TABLE 9-12: Pin Name RF0/AN5/ SEG18 RF1/AN6/ C2OUT/SEG19 RF2/AN7/ C1OUT/SEG20 RF3/AN8/ SEG21 RF4/AN9/ SEG22 RF5/AN10/ CVREF/SEG23 RF6/AN11/ SEG24 RF7/SS/SEG25 Legend: PORTF FUNCTIONS Function TRIS Setting I/O Buffer Description RF0 0 O DIG LATF<0> data output. Output is unaffected by analog input; disabled when LCD segment is enabled. 1 I ST PORTF<0> data input. Reads ‘0’ on POR. AN5 1 I ANA A/D input channel 5. Default configuration on POR.
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PIC18F6390/6490/8390/8490 TABLE 9-13: Name TRISF SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page PORTF Data Direction Register 62 PORTF Read PORTF Data Latch/Write PORTF Data Latch 62 LATF LATF Data Output Register 62 ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 61 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 61 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 61 LCDSE2 SE23 SE22 SE21 SE20
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PIC18F6390/6490/8390/8490 9.7 PORTG, TRISG and LATG Registers PORTG is a 6-bit wide, bidirectional port. The corresponding Data Direction register is TRISG. Setting a TRISG bit (= 1) will make the corresponding PORTG pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISG bit (= 0) will make the corresponding PORTG pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATG) is also memory mapped.
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PIC18F6390/6490/8390/8490 TABLE 9-14: Pin Name PORTG FUNCTIONS Function TRIS Setting I/O Buffer RG0 0 O DIG LATG<0> data output; disabled when LCD segment enabled. 1 I ST PORTG<0> data input. RG0/SEG30 SEG30 x O ANA Segment 30 analog output for LCD. RG1 0 O DIG LATG<1> data output; disabled when LCD segment enabled. RG1/TX2/CK2/ SEG29 ST PORTG<1> data input. O DIG Synchronous serial data output (AUSART module); takes priority over port data.
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PIC18F6390/6490/8390/8490 9.8 Note: PORTH, LATH and TRISH Registers PORTH is available only on 80-pin devices. PORTH is an 8-bit wide, bidirectional I/O port. The corresponding Data Direction register is TRISH. Setting a TRISH bit (= 1) will make the corresponding PORTH pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISH bit (= 0) will make the corresponding PORTH pin an output (i.e., put the contents of the output latch on the selected pin).
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PIC18F6390/6490/8390/8490 TABLE 9-16: Pin Name PORTH FUNCTIONS Function TRIS Setting I/O Buffer RH0 0 O DIG-4 1 I ST SEG47 x O ANA Segment 47 analog output for LCD. RH1 0 O DIG LATH<1> data output; disabled when LCD segment enabled. RH0/SEG47 RH1/SEG46 RH2/SEG45 RH3/SEG44 RH4/SEG40 RH5/SEG41 RH6/SEG42 RH7/SEG43 TRISH PORTH<0> data input. 1 I ST x O ANA Segment 46 analog output for LCD. PORTH<1> data input.
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PIC18F6390/6490/8390/8490 9.9 Note: PORTJ, TRISJ and LATJ Registers EXAMPLE 9-9: CLRF PORTJ CLRF LATJ PORTJ is available only on 80-pin devices. PORTJ is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISJ. Setting a TRISJ bit (= 1) will make the corresponding PORTJ pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISJ bit (= 0) will make the corresponding PORTJ pin an output (i.e.
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PIC18F6390/6490/8390/8490 TABLE 9-18: Pin Name PORTJ FUNCTIONS Function TRIS Setting I/O Buffer RJ0 0 O DIG 1 I ST SEG32 x O ANA Segment 32 analog output for LCD. RJ1 0 O DIG LATJ<1> data output; disabled when LCD segment enabled. RJ0/SEG32 RJ1/SEG33 RJ2/SEG34 RJ3/SEG35 RJ4/SEG39 RJ5/SEG38 RJ6/SEG37 RJ7/SEG36 PORTJ PORTJ<0> data input. 1 I ST x O ANA Segment 33 analog output for LCD. PORTJ<1> data input.
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PIC18F6390/6490/8390/8490 10.0 TIMER0 MODULE The Timer0 module incorporates the following features: • Software selectable operation as a timer or counter in both 8-bit or 16-bit modes • Readable and writable registers • Dedicated 8-bit software programmable prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow REGISTER 10-1: The T0CON register (Register 10-1) controls all aspects of the module’s operation, including the prescale selection.
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PIC18F6390/6490/8390/8490 10.1 Timer0 Operation Timer0 can operate as either a timer or a counter; the mode is selected by clearing the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default, unless a different prescaler value is selected (see Section 10.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register.
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PIC18F6390/6490/8390/8490 10.3 Prescaler 10.3.1 An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable; its value is set by the PSA and T0PS2:T0PS0 bits (T0CON<3:0>), which determine the prescaler assignment and prescale ratio. Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values from 1:2 through 1:256 in power-of-2 increments are selectable.
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PIC18F6390/6490/8390/8490 11.
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PIC18F6390/6490/8390/8490 11.1 Timer1 Operation cycle (FOSC/4). When the bit is set, Timer1 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter When Timer1 is enabled, the RC1/T1OSI and RC0/T1OSO/T13CKI pins become inputs. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’.
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PIC18F6390/6490/8390/8490 11.2 Timer1 16-Bit Read/Write Mode Timer1 can be configured for 16-bit reads and writes (see Figure 11-2). When the RD16 control bit (T1CON<7>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 High Byte Buffer register.
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PIC18F6390/6490/8390/8490 11.3.3 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 11-3, should be located as close as possible to the microcontroller. There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD.
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PIC18F6390/6490/8390/8490 EXAMPLE 11-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BSF RETURN 80h TMR1H TMR1L b’00001111’ T1OSC secs mins .12 hours PIE1, TMR1IE BSF BCF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN MOVLW MOVWF RETURN TMR1H, 7 PIR1, TMR1IF secs, F .
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PIC18F6390/6490/8390/8490 12.0 TIMER2 MODULE 12.
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PIC18F6390/6490/8390/8490 12.2 Timer2 Interrupt 12.3 Timer2 also can generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) provides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1<1>).
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PIC18F6390/6490/8390/8490 13.0 TIMER3 MODULE The Timer3 timer/counter module incorporates these features: • Software selectable operation as a 16-bit timer or counter • Readable and writable 8-bit registers (TMR3H and TMR3L) • Selectable clock source (internal or external), with device clock or Timer1 oscillator internal options • Interrupt-on-overflow • Module Reset on CCP Special Event Trigger REGISTER 13-1: A simplified block diagram of the Timer3 module is shown in Figure 13-1.
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PIC18F6390/6490/8390/8490 13.1 Timer3 Operation cycle (FOSC/4). When the bit is set, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. Timer3 can operate in one of three modes: • Timer • Synchronous counter • Asynchronous counter As with Timer1, the RC1/T1OSI and RC0/T1OSO/T13CKI pins become inputs when the Timer1 oscillator is enabled. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’.
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PIC18F6390/6490/8390/8490 13.2 Timer3 16-Bit Read/Write Mode 13.4 Timer3 Interrupt Timer3 can be configured for 16-bit reads and writes (see Figure 13-2). When the RD16 control bit (T3CON<7>) is set, the address for TMR3H is mapped to a buffer register for the high byte of Timer3. A read from TMR3L will load the contents of the high byte of Timer3 into the Timer3 High Byte Buffer register.
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PIC18F6390/6490/8390/8490 14.0 CAPTURE/COMPARE/PWM (CCP) MODULES PIC18F6390/6490/8390/8490 devices have two CCP (Capture/Compare/PWM) modules, designated CCP1 and CCP2. Both modules implement standard capture, compare and Pulse-Width Modulation (PWM) modes. REGISTER 14-1: Each CCP module contains a 16-bit register which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register.
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PIC18F6390/6490/8390/8490 14.1 CCP Module Configuration The assignment of a particular timer to a module is determined by the Timer to CCP enable bits in the T3CON register (Register 13-1). Both modules may be active at any given time and may share the same timer resource if they are configured to operate in the same mode (capture/compare or PWM) at the same time. The interactions between the two modules are summarized in Table 14-2.
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PIC18F6390/6490/8390/8490 TABLE 14-2: INTERACTIONS BETWEEN CCP1 AND CCP2 FOR TIMER RESOURCES CCP1 Mode CCP2 Mode Interaction Capture Capture Each module can use TMR1 or TMR3 as the time base. The time base can be different for each CCP. Capture Compare CCP2 can be configured for the Special Event Trigger to reset TMR1 or TMR3 (depending upon which time base is used). Automatic A/D conversions on trigger event can also be done.
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PIC18F6390/6490/8390/8490 14.2 Capture Mode 14.2.3 SOFTWARE INTERRUPT In Capture mode, the CCPR2H:CCPR2L register pair captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on the CCP2 pin (RC1 or RE7, depending on device configuration). An event is defined as one of the following: When the Capture mode is changed, a false capture interrupt may be generated.
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PIC18F6390/6490/8390/8490 14.3 Compare Mode 14.3.3 SOFTWARE INTERRUPT MODE In Compare mode, the 16-bit CCPR2 register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCP2 pin can be: When the Generate Software Interrupt mode is chosen (CCP2M3:CCP2M0 = 1010), the CCP2 pin is not affected. Only a CCP interrupt is generated if enabled and the CCP2IE bit is set. • • • • 14.3.
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PIC18F6390/6490/8390/8490 TABLE 14-3: Name INTCON REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page INT0IE RBIE TMR0IF INT0IF RBIF 59 IPEN SBOREN — RI TO PD POR BOR 60 PIR1 — ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 61 PIE1 — ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 61 IPR1 — ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 61 RCON PIR2 OSCFIF
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PIC18F6390/6490/8390/8490 14.4 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCP2 pin produces up to a 10-bit resolution PWM output. Since the CCP2 pin is multiplexed with a PORTC or PORTE data latch, the appropriate TRIS bit must be cleared to make the CCP2 pin an output. Note: A PWM output (Figure 14-5) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).
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PIC18F6390/6490/8390/8490 14.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR2L register and to the CCP2CON<5:4> bits. Up to 10-bit resolution is available. The CCPR2L contains the eight MSbs and the CCP2CON<5:4> bits contain the two LSbs. This 10-bit value is represented by CCPR2L:CCP2CON<5:4>.
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PIC18F6390/6490/8390/8490 14.4.3 SETUP FOR PWM OPERATION 3. The following steps should be taken when configuring the CCP2 module for PWM operation: 1. 2. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR2L register and CCP2CON<5:4> bits. TABLE 14-5: Name INTCON 4. 5. Make the CCP2 pin an output by clearing the appropriate TRIS bit. Set the TMR2 prescale value, then enable Timer2 by writing to T2CON. Configure the CCP2 module for PWM operation.
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PIC18F6390/6490/8390/8490 15.0 15.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc.
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PIC18F6390/6490/8390/8490 15.3.1 REGISTERS SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. The MSSP module has four registers for SPI mode operation. These are: • • • • In receive operations, SSPSR and SSPBUF together create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set.
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PIC18F6390/6490/8390/8490 REGISTER 15-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV(1) SSPEN(2) CKP SSPM3(3) SSPM2(3) SSPM1(3) SSPM0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmittin
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PIC18F6390/6490/8390/8490 15.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
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PIC18F6390/6490/8390/8490 15.3.3 ENABLING SPI I/O 15.3.4 To enable the serial port, MSSP Enable bit, SSPEN (SSPCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPCONx registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins.
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PIC18F6390/6490/8390/8490 15.3.5 MASTER MODE The clock polarity is selected by appropriately programming the CKP bit (SSPCON1<4>). This then, would give waveforms for SPI communication, as shown in Figure 15-3, Figure 15-5 and Figure 15-6, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: The master can initiate the data transfer at any time because it controls the SCK.
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PIC18F6390/6490/8390/8490 15.3.6 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data.
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PIC18F6390/6490/8390/8490 FIGURE 15-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle after Q2↓ SSPSR to SSPBUF FIGURE 15-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 7 bit 6 bit
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PIC18F6390/6490/8390/8490 15.3.8 SLEEP OPERATION 15.3.9 In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of Sleep mode, all clocks are halted. In most power-managed modes, a clock is provided to the peripherals. That clock should be from the primary clock source, the secondary clock (Timer1 oscillator at 32.768 kHz) or the INTOSC source. See Section 2.7 “Clock Sources and Oscillator Switching” for additional information.
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PIC18F6390/6490/8390/8490 15.4 I2C Mode 15.4.1 The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing.
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PIC18F6390/6490/8390/8490 REGISTER 15-3: SSPSTAT: MSSP STATUS REGISTER (I2C™ MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P(1) S(1) R/W(2,3) UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled f
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PIC18F6390/6490/8390/8490 REGISTER 15-4: R/W-0 SSPCON1: MSSP CONTROL REGISTER 1 (I2C™ MODE) R/W-0 WCOL SSPOV R/W-0 SSPEN (1) R/W-0 CKP R/W-0 SSPM3 (2) R/W-0 SSPM2 (2) R/W-0 SSPM1 (2) R/W-0 SSPM0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPxBUF register was attempted while the I
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PIC18F6390/6490/8390/8490 REGISTER 15-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in
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PIC18F6390/6490/8390/8490 15.4.2 OPERATION The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON1<5>). The SSPCON1 register allows control of the I 2C operation.
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PIC18F6390/6490/8390/8490 15.4.3.2 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set, or bit SSPOV (SSPCON1<6>) is set.
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DS39629C-page 172 CKP (SSPCON1<4>) SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) SSPIF (PIR1<3>) 1 SCL S A7 3 4 A4 5 A3 Receiving Address A5 6 A2 7 A1 8 9 ACK R/W = 0 (CKP does not reset to ‘0’ when SEN = 0) 2 A6 1 D7 3 4 D4 5 D3 Receiving Data D5 Cleared in software SSPBUF is read 2 D6 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 4 D4 5 D3 Receiving Data D5 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPBUF is still full. ACK is not sent.
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DS39629C-page 174 2 1 3 1 4 1 5 0 7 A8 UA is set indicating that the SSPADD needs to be updated 8 9 (CKP does not reset to ‘0’ when SEN = 0) CKP (SSPCON1<4>) UA (SSPSTAT<1>) SSPOV (SSPCON1<6>) 6 A9 SSPBUF is written with contents of SSPSR Cleared in software BF (SSPSTAT<0>) SSPIF (PIR1<3>) 1 SCL S 1 ACK R/W = 0 A7 2 4 A4 5 A3 6 8 9 A0 ACK UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address 7 A2 A1
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PIC18F6390/6490/8390/8490 15.4.4 CLOCK STRETCHING Both 7 and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence. 15.4.4.
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PIC18F6390/6490/8390/8490 15.4.4.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCL output is forced to ‘0’. However, setting the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has FIGURE 15-12: already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL.
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DS39629C-page 178 CKP (SSPON1<4>) SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) SSPIF (PIR1<3>) 1 SCL S A7 2 A6 3 4 A4 5 A3 6 A2 Receiving Address A5 7 A1 8 9 ACK R/W = 0 3 4 D4 5 D3 Receiving Data D5 Cleared in software 2 D6 If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to ‘0’ and no clock stretching will occur SSPBUF is read 1 D7 6 D2 7 D1 9 ACK 1 D7 BF is set after falling edge of the 9th clock, CKP is reset to ‘0’ and clock stretchi
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PIC18F6390/6490/8390/8490 15.4.5 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices.
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PIC18F6390/6490/8390/8490 MASTER MODE Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled.
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PIC18F6390/6490/8390/8490 15.4.6.1 I2C Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock.
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PIC18F6390/6490/8390/8490 15.4.7 BAUD RATE 2 In I C Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPADD register (Figure 15-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to 0 and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically.
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PIC18F6390/6490/8390/8490 15.4.7.1 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the FIGURE 15-18: SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and begins counting.
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PIC18F6390/6490/8390/8490 15.4.8 I2C MASTER MODE START CONDITION TIMING Note: To initiate a Start condition, the user sets the Start Condition Enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low.
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PIC18F6390/6490/8390/8490 15.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and the I2C logic module is in the Idle state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded with the contents of SSPADD<5:0> and begins counting.
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PIC18F6390/6490/8390/8490 15.4.10 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification parameter #106).
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DS39629C-page 188 S R/W PEN SEN BF (SSPSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared in software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPBUF written 1 D7 1 SCL held low while CPU responds to SSPIF ACK = 0 R/W = 0 SSPBUF written with 7-bit address and R/W start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPBUF is written in software Cleared in software service routine from MSSP interrupt 2 D6 Transmitting Da
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PIC18F6390/6490/8390/8490 15.4.12 ACKNOWLEDGE SEQUENCE TIMING 15.4.13 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPCON2<2>). At the end of a receive/ transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’.
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PIC18F6390/6490/8390/8490 15.4.14 SLEEP OPERATION 15.4.17 2 While in Sleep mode, the I C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 15.4.15 EFFECT OF A RESET A Reset disables the MSSP module and terminates the current transfer. 15.4.
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PIC18F6390/6490/8390/8490 15.4.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 15-26). SCL is sampled low before SDA is asserted low (Figure 15-27). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 15-28).
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PIC18F6390/6490/8390/8490 FIGURE 15-27: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF.
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PIC18F6390/6490/8390/8490 15.4.17.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 15-29). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time.
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PIC18F6390/6490/8390/8490 15.4.17.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 15-31).
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PIC18F6390/6490/8390/8490 TABLE 15-4: Name INTCON REGISTERS ASSOCIATED WITH I2C™ OPERATION Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 59 PIR1 — ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 61 PIE1 — ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 61 — ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP IPR1 TRISC PORTC Data Direction Register SSPBUF MSSP Receive Buffer/Transmit Register SS
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PIC18F6390/6490/8390/8490 16.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) PIC18F6390/6490/8390/8490 devices have three serial I/O modules: the MSSP module, discussed in the previous chapter and two Universal Synchronous Asynchronous Receiver Transmitter (USART) modules. (Generically, the USART is also known as a Serial Communications Interface or SCI.
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PIC18F6390/6490/8390/8490 REGISTER 16-1: TXSTA1: EUSART TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care.
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PIC18F6390/6490/8390/8490 REGISTER 16-2: RCSTA1: EUSART RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX1/DT1 and TX1/CK1 pins as serial port pins) 0 = Serial port disabled (hel
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PIC18F6390/6490/8390/8490 REGISTER 16-3: BAUDCON1: BAUD RATE CONTROL REGISTER 1 R/W-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No B
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PIC18F6390/6490/8390/8490 16.1 EUSART Baud Rate Generator (BRG) The BRG is a dedicated, 8-bit or 16-bit generator that supports both the Asynchronous and Synchronous modes of the EUSART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCON1<3>) selects 16-bit mode. The SPBRGH1:SPBRG1 register pair controls the period of a free-running timer. In Asynchronous mode, the BRGH (TXSTA1<2>) and BRG16 (BAUDCON1<3>) bits also control the baud rate. In Synchronous mode, BRGH is ignored.
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PIC18F6390/6490/8390/8490 TABLE 16-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) % Error FOSC = 20.000 MHz SPBRG Actual value Rate (K) (decimal) % Error FOSC = 10.000 MHz SPBRG Actual value Rate (K) (decimal) % Error FOSC = 8.000 MHz SPBRG Actual value Rate (K) (decimal) % Error SPBRG value (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103 2.4 2.441 1.
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PIC18F6390/6490/8390/8490 TABLE 16-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) % Error FOSC = 20.000 MHz SPBRG Actual value Rate (K) (decimal) % Error FOSC = 10.000 MHz SPBRG Actual value Rate (K) (decimal) % Error FOSC = 8.000 MHz SPBRG Actual value Rate (K) (decimal) % Error SPBRG value (decimal) 0.3 1.2 0.300 1.200 0.00 0.02 8332 2082 0.300 1.200 0.02 -0.03 4165 1041 0.300 1.200 0.02 -0.
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PIC18F6390/6490/8390/8490 16.1.3 AUTO-BAUD RATE DETECT The Enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. Note 1: If the WUE bit is set with the ABDEN bit, Auto-Baud Rate Detection will occur on the byte following the Break character. 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source.
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PIC18F6390/6490/8390/8490 FIGURE 16-1: BRG Value AUTOMATIC BAUD RATE CALCULATION XXXXh 0000h 001Ch Start RX1 pin Edge #1 Bit 1 Bit 0 Edge #2 Bit 3 Bit 2 Edge #3 Bit 5 Bit 4 Edge #4 Bit 7 Bit 6 Edge #5 Stop Bit BRG Clock Auto-Cleared Set by User ABDEN bit RC1IF bit (Interrupt) Read RCREG1 SPBRG1 XXXXh 1Ch SPBRGH1 XXXXh 00h Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
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PIC18F6390/6490/8390/8490 16.2 EUSART Asynchronous Mode Once the TXREG1 register transfers the data to the TSR register (occurs in one TCY), the TXREG1 register is empty and the TX1IF flag bit (PIR1<4>) is set. This interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TX1IE (PIE1<4>). TX1IF will be set regardless of the state of TX1IE; it cannot be cleared in software.
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PIC18F6390/6490/8390/8490 FIGURE 16-4: ASYNCHRONOUS TRANSMISSION Write to TXREG1 Word 1 BRG Output (Shift Clock) TX1 (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TX1IF bit (Transmit Buffer Reg. Empty Flag) 1 TCY Word 1 Transmit Shift Reg TRMT bit (Transmit Shift Reg. Empty Flag) FIGURE 16-5: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG1 Word 2 Word 1 BRG Output (Shift Clock) TX1 (pin) Start bit bit 1 1 TCY TX1IF bit (Interrupt Reg.
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PIC18F6390/6490/8390/8490 16.2.2 EUSART ASYNCHRONOUS RECEIVER 16.2.3 The receiver block diagram is shown in Figure 16-6. The data is received on the RX1 pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. This mode would typically be used in RS-485 systems.
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PIC18F6390/6490/8390/8490 FIGURE 16-7: ASYNCHRONOUS RECEPTION Start bit RX1 (pin) bit 0 bit 1 bit 7/8 Stop bit Rcv Shift Reg Rcv Buffer Reg Start bit bit 0 Stop bit Start bit bit 7/8 Stop bit Word 2 RCREG1 Word 1 RCREG1 RCREG1 Read Rcv Buffer Reg bit 7/8 RC1IF (Interrupt Flag) OERR bit CREN bit Note: This timing diagram shows three words appearing on the RX1 input. The RCREG1 (Receive Buffer register) is read after the third word causing the OERR (Overrun) bit to be set.
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PIC18F6390/6490/8390/8490 16.2.4 AUTO-WAKE-UP ON SYNC BREAK CHARACTER During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be performed. The auto-wake-up feature allows the controller to wake-up, due to activity on the RX1/DT1 line, while the EUSART is operating in Asynchronous mode. The auto-wake-up feature is enabled by setting the WUE bit (BAUDCON<1>).
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PIC18F6390/6490/8390/8490 16.2.5 BREAK CHARACTER SEQUENCE The Enhanced USART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. The Break character transmit consists of a Start bit, followed by twelve ‘0’ bits and a Stop bit. The Frame Break character is sent whenever the SENDB and TXEN bits (TXSTA<3> and TXSTA<5>) are set while the Transmit Shift Register is loaded with data.
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PIC18F6390/6490/8390/8490 16.3 EUSART Synchronous Master Mode Once the TXREG1 register transfers the data to the TSR register (occurs in one TCYCLE), the TXREG1 is empty and the TX1IF flag bit (PIR1<4>) is set. The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TX1IE (PIE1<4>). TX1IF is set regardless of the state of enable bit, TX1IE; it cannot be cleared in software. It will reset only when new data is loaded into the TXREG1 register.
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PIC18F6390/6490/8390/8490 FIGURE 16-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX1/DT1 pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX1/CK1 pin Write to TXREG1 Reg TX1IF bit TRMT bit TXEN bit TABLE 16-7: Name INTCON REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page INT0IE RBIE TMR0IF INT0IF RBIF 59 PIR1 — ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 61 PIE1 — ADIE RC1
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PIC18F6390/6490/8390/8490 16.3.2 EUSART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTA1<5>), or the Continuous Receive Enable bit, CREN (RCSTA1<4>). Data is sampled on the RX1 pin on the falling edge of the clock. If enable bit, SREN, is set, only a single word is received. If enable bit, CREN, is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence.
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PIC18F6390/6490/8390/8490 16.4 EUSART Synchronous Slave Mode Synchronous Slave mode is entered by clearing bit, CSRC (TXSTA1<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CK1 pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 16.4.
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PIC18F6390/6490/8390/8490 16.4.2 EUSART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical except in the case of Sleep or any Idle mode and bit, SREN, which is a “don’t care” in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode.
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PIC18F6390/6490/8390/8490 17.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (AUSART) The Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) module is very similar in function to the Enhanced USART module, discussed in the previous chapter. It is provided as an additional channel for serial communication, with external devices, for those situations that do not require Auto-Baud Detection or LIN bus support.
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PIC18F6390/6490/8390/8490 REGISTER 17-1: TXSTA2: AUSART TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC — BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care.
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PIC18F6390/6490/8390/8490 REGISTER 17-2: RCSTA2: AUSART RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX2/DT2 and TX2/CK2 pins as serial port pins) 0 = Serial port disabled (hel
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PIC18F6390/6490/8390/8490 17.1 AUSART Baud Rate Generator (BRG) geous to use the high baud rate (BRGH = 1) to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. The BRG is a dedicated 8-bit generator that supports both the Asynchronous and Synchronous modes of the AUSART. The SPBRG2 register controls the period of a free-running timer. In Asynchronous mode, bit BRGH (TXSTA<2>) also controls the baud rate. In Synchronous mode, BRGH is ignored.
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PIC18F6390/6490/8390/8490 TABLE 17-3: BAUD RATES FOR ASYNCHRONOUS MODES BRGH = 0 FOSC = 40.000 MHz BAUD RATE (K) Actual Rate (K) % Error FOSC = 20.000 MHz SPBRG Actual value Rate (K) (decimal) % Error FOSC = 10.000 MHz SPBRG Actual value Rate (K) (decimal) % Error FOSC = 8.000 MHz SPBRG Actual value Rate (K) (decimal) % Error SPBRG value (decimal) 0.3 — — — — — — — — — — — — 1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103 2.4 2.441 1.73 255 2.404 0.
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PIC18F6390/6490/8390/8490 17.2 AUSART Asynchronous Mode Once the TXREG2 register transfers the data to the TSR register (occurs in one TCY), the TXREG2 register is empty and the TX2IF flag bit (PIR3<4>) is set. This interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TX2IE (PIE3<4>). TX2IF will be set regardless of the state of TX2IE; it cannot be cleared in software.
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PIC18F6390/6490/8390/8490 FIGURE 17-2: ASYNCHRONOUS TRANSMISSION Write to TXREG2 Word 1 BRG Output (Shift Clock) TX2 (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TX2IF bit (Transmit Buffer Reg. Empty Flag) 1 TCY Word 1 Transmit Shift Reg TRMT bit (Transmit Shift Reg. Empty Flag) FIGURE 17-3: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG2 Word 2 Word 1 BRG Output (Shift Clock) TX2 (pin) Start bit bit 1 1 TCY TX2IF bit (Interrupt Reg.
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PIC18F6390/6490/8390/8490 17.2.2 AUSART ASYNCHRONOUS RECEIVER 17.2.3 The receiver block diagram is shown in Figure 17-4. The data is received on the RX2 pin and drives the data recovery block. The data recovery block is actually a high-speed shifter, operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. This mode would typically be used in RS-485 systems.
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PIC18F6390/6490/8390/8490 FIGURE 17-5: ASYNCHRONOUS RECEPTION Start bit bit 0 RX2 (pin) bit 1 Start bit bit 7/8 Stop bit Rcv Shift Reg Rcv Buffer Reg bit 0 Stop bit Start bit bit 7/8 Stop bit Word 2 RCREG2 Word 1 RCREG2 Read Rcv Buffer Reg RCREG2 bit 7/8 RC2IF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX2 input. The RCREG2 (Receive Buffer register) is read after the third word causing the OERR (Overrun) bit to be set.
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PIC18F6390/6490/8390/8490 17.3 AUSART Synchronous Master Mode Once the TXREG2 register transfers the data to the TSR register (occurs in one TCYCLE), the TXREG2 is empty and the TX2IF flag bit (PIR3<4>) is set. The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TX2IE (PIE3<4>). TX2IF is set regardless of the state of enable bit, TX2IE; it cannot be cleared in software. It will reset only when new data is loaded into the TXREG2 register.
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PIC18F6390/6490/8390/8490 FIGURE 17-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX2/DT2 pin bit 0 bit 1 bit 2 bit 6 bit 7 TX2/CK2 pin Write to TXREG2 Reg TX2IF bit TRMT bit TXEN bit TABLE 17-6: Name INTCON REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page INT0IE RBIE TMR0IF INT0IF RBIF 59 PIR3 — LCDIF RC2IF TX2IF — — — — 61 PIE3 — LCDIE RC2IE TX2IE — — — — 61 IPR3 — LCDIP RC2IP TX2IP —
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PIC18F6390/6490/8390/8490 17.3.2 AUSART SYNCHRONOUS MASTER RECEPTION 4. 5. 6. If interrupts are desired, set enable bit, RC2IE. If 9-bit reception is desired, set bit, RX9. If a single reception is required, set bit, SREN. For continuous reception, set bit, CREN. 7. Interrupt flag bit, RC2IF, will be set when reception is complete and an interrupt will be generated if the enable bit, RC2IE, was set. 8.
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PIC18F6390/6490/8390/8490 17.4 AUSART Synchronous Slave Mode Synchronous Slave mode is entered by clearing bit, CSRC (TXSTA2<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CK2 pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 17.4.
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PIC18F6390/6490/8390/8490 17.4.2 AUSART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical except in the case of Sleep, or any Idle mode and bit SREN, which is a “don’t care” in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep, or any Idle mode, then a word may be received while in this low-power mode.
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PIC18F6390/6490/8390/8490 18.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The Analog-to-Digital (A/D) converter module has 12 inputs for the PIC18F6X90/8X90 devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number.
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PIC18F6390/6490/8390/8490 REGISTER 18-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-q R/W-q R/W-q R/W-q — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared PCFG3: PCFG0 AN5 AN4 AN3 AN2 AN1 AN0 PCFG3:PCFG0: A/D Port Configuration Control bits: AN6 bit 3-0 AN7 VCFG0: Voltage Reference Configuration bit (VREF+ source) 1 = VREF+ (AN3
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PIC18F6390/6490/8390/8490 REGISTER 18-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits 111 = 20
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PIC18F6390/6490/8390/8490 The analog reference voltage is software selectable to either the device’s positive and negative supply voltage (AVDD and AVSS), or the voltage level on the RA3/AN3/VREF+/SEG17 and RA2/AN2/VREF-/SEG16 pins. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted. Each port pin associated with the A/D converter can be configured as an analog input or as a digital I/O.
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PIC18F6390/6490/8390/8490 Wait for A/D conversion to complete, by either: • Polling for the GO/DONE bit to be cleared OR 6. 7. • Waiting for the A/D interrupt Read A/D Result registers (ADRESH:ADRESL); clear ADIF bit, if required. For next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 3 TAD is required before the next acquisition starts. FIGURE 18-2: The following steps should be followed to perform an A/D conversion: 3FFh 1.
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PIC18F6390/6490/8390/8490 18.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 18-3. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD).
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PIC18F6390/6490/8390/8490 18.2 Selecting and Configuring Automatic Acquisition Time The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit.
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PIC18F6390/6490/8390/8490 18.4 Operation in Power-Managed Modes The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode. If the A/D is expected to operate while the device is in a power-managed mode, the ACQT2:ACQT0 and ADCS2:ADCS0 bits in ADCON2 should be updated in accordance with the power-managed mode clock that will be used.
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PIC18F6390/6490/8390/8490 18.6 A/D Conversions After the A/D conversion is completed or aborted, a 2 TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. Figure 18-4 shows the operation of the A/D converter after the GO/DONE bit has been set and the ACQT2:ACQT0 bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins.
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PIC18F6390/6490/8390/8490 18.8 Use of the CCP2 Trigger An A/D conversion can be started by the “Special Event Trigger” of the CCP2 module. This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as ‘1011’ and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D acquisition and conversion and the Timer1 (or Timer3) counter will be reset to zero.
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PIC18F6390/6490/8390/8490 19.0 COMPARATOR MODULE The analog comparator module contains two comparators that can be configured in a variety of ways. The inputs can be selected from the analog inputs multiplexed with pins RF3 through RF6, as well as the on-chip voltage reference (see Section 20.0 “Comparator Voltage Reference Module”). The digital outputs (normal or inverted) are available at the pin level and can also be read through the control register.
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PIC18F6390/6490/8390/8490 19.1 Comparator Configuration There are eight modes of operation for the comparators, shown in Figure 19-1. Bits, CM2:CM0 of the CMCON register, are used to select these modes. The TRISF register controls the data direction of the comparator pins for each mode. If the Comparator FIGURE 19-1: RF4/AN9/ SEG22 RF3/AN8/ SEG21 A A Note: Comparator interrupts should be disabled during a Comparator mode change; otherwise, a false interrupt may occur.
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PIC18F6390/6490/8390/8490 19.2 Comparator Operation 19.3.2 INTERNAL REFERENCE SIGNAL A single comparator is shown in Figure 19-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level.
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PIC18F6390/6490/8390/8490 + To RF2 or RF1 pin - Port pins COMPARATOR OUTPUT BLOCK DIAGRAM MULTIPLEX FIGURE 19-3: D Q Bus Data CxINV Read CMCON EN D Q EN CL From Other Comparator Reset 19.6 Comparator Interrupts The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred.
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PIC18F6390/6490/8390/8490 19.9 Analog Input Connection Considerations range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10 kΩ is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current. A simplified circuit for an analog input is shown in Figure 19-4.
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PIC18F6390/6490/8390/8490 20.0 COMPARATOR VOLTAGE REFERENCE MODULE The comparator voltage reference is a 16-tap resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it may also be used independently of them. A block diagram of the module is shown in Figure 20-1.
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PIC18F6390/6490/8390/8490 FIGURE 20-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ VDD CVRSS = 1 8R CVRSS = 0 CVR3:CVR0 R CVREN R R 16-to-1 MUX R 16 Steps R CVREF R R CVRR VREF- 8R CVRSS = 1 CVRSS = 0 20.2 Voltage Reference Accuracy/Error The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 20-1) keep CVREF from approaching the reference source rails.
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PIC18F6390/6490/8390/8490 FIGURE 20-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18FXXXX CVREF Module R(1) Voltage Reference Output Impedance Note 1: TABLE 20-1: Name CVREF Output R is dependent upon the voltage reference configuration bits, CVRCON<3:0> and CVRCON<5>.
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PIC18F6390/6490/8390/8490 21.0 HIGH/LOW-VOLTAGE DETECT (HLVD) PIC18F6390/6490/8390/8490 devices have a High/Low-Voltage Detect module (HLVD). This is a programmable circuit that allows the user to specify both a device voltage trip point and the direction of change from that point. If the device experiences an excursion past the trip point in that direction, an interrupt flag is set.
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PIC18F6390/6490/8390/8490 The module is enabled by setting the HLVDEN bit. Each time that the HLVD module is enabled, the circuitry requires some time to stabilize. The IRVST bit is a read-only bit and is used to indicate when the circuit is stable. The module can only generate an interrupt after the circuit is stable and IRVST is set. event, depending on the configuration of the module.
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PIC18F6390/6490/8390/8490 21.2 HLVD Setup Depending on the application, the HLVD module does not need to be operating constantly. To decrease the current requirements, the HLVD circuitry may only need to be enabled for short periods where the voltage is checked. After doing the check, the HLVD module may be disabled. The following steps are needed to set up the HLVD module: 1. 2. 3. 4. 5. 6. Disable the module by clearing the HLVDEN bit (HLVDCON<4>).
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PIC18F6390/6490/8390/8490 FIGURE 21-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1) CASE 1: HLVDIF may not be set VLVD VDD HLVDIF Enable HLVD TIRVST IRVST HLVDIF cleared in software Internal Reference is stable CASE 2: VLVD VDD HLVDIF Enable HLVD TIRVST IRVST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists Applications In many applications, the ability to detect a drop below, or rise above a particular threshol
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PIC18F6390/6490/8390/8490 21.6 Operation During Sleep 21.7 When enabled, the HLVD circuitry continues to operate during Sleep. If the device voltage crosses the trip point, the HLVDIF bit will be set and the device will wake-up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. TABLE 21-1: Effects of a Reset A device Reset forces all registers to their Reset state. This forces the HLVD module to be turned off.
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PIC18F6390/6490/8390/8490 22.0 LIQUID CRYSTAL DISPLAY (LCD) DRIVER MODULE The Liquid Crystal Display (LCD) driver module generates the timing control to drive a static or multiplexed LCD panel. In the 80-pin devices (PIC18F8390/8490), the module drives the panels of up to four commons and up to 48 segments and in the 64-pin devices (PIC18F6390/6490), the module drives the panels of up to four commons and up to 32 segments. It also provides control of the LCD pixel data.
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PIC18F6390/6490/8390/8490 22.1 LCD Registers The LCD driver module has 32 registers: used to enable or disable the LCD module. The LCD panel can also operate during Sleep by clearing the SLPEN (LCDCON<6>) bit. • LCD Control Register (LCDCON) • LCD Phase Register (LCDPS) • Six LCD Segment Enable Registers (LCDSE5:LCDSE0) • 24 LCD Data Registers (LCDDATA23:LCDDATA0) The LCDPS register, shown in Register 22-2, configures the LCD clock source prescaler and the type of waveform, Type-A or Type-B.
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PIC18F6390/6490/8390/8490 REGISTER 22-2: LCDPS: LCD PHASE REGISTER R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 WFT BIASMD LCDA WA LP3 LP2 LP1 LP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WFT: Waveform Type Select bit 1 = Type-B waveform (phase changes on each frame boundary) 0 = Type-A waveform (phase changes within each common type) bit 6 BIASMD: Bias Mode Select bit Wh
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PIC18F6390/6490/8390/8490 The LCDSE5:LCDSE0 registers configure the functions of the port pins. Setting the segment enable bit for a particular segment configures that pin as an LCD driver. There are six LCD Segment Enable registers listed in Table 22-1. The prototype LCDSEx register is shown in Register 22-3.
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PIC18F6390/6490/8390/8490 TABLE 22-2: LCDDATA REGISTERS AND BITS FOR SEGMENT AND COM COMBINATIONS COM Lines Segments 0 through 7 8 through 15 16 through 23 24 through 31 32 through 39 40 through 47 Note 1: 0 1 2 3 LCDDATA0 LCDDATA6 LCDDATA12 LCDDATA18 S00C0:S07C0 S00C1:S07C1 S00C2:S07C2 S00C3:S07C3 LCDDATA1 LCDDATA7 LCDDATA13 LCDDATA19 S08C0:S15C0 S08C1:S15C1 S08C2:S15C2 S08C0:S15C3 LCDDATA2 LCDDATA8 LCDDATA14 LCDDATA20 S16C0:S23C0 S16C1:S23C1 S16C2:S23C2 S16C3:S23C3 LCDDATA3
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PIC18F6390/6490/8390/8490 22.2 LCD Clock Source Selection The LCD driver module has 3 possible clock sources: The third clock source is a 31.25 kHz internal RC oscillator/32, which provides approximately 1 kHz output. • (FOSC/4)/8192 • T13CKI Clock/32 • INTRC/32 The second and third clock sources may be used to continue running the LCD while the processor is in Sleep. The first clock source is the system clock divided by 8192 ((FOSC/4)/8192).
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PIC18F6390/6490/8390/8490 22.3 LCD Bias Types The LCD driver module can be configured into three bias types: • Static Bias (2 voltage levels: AVSS and AVDD) • 1/2 Bias (3 voltage levels: AVSS, 1/2 AVDD and AVDD) • 1/3 Bias (4 voltage levels: AVSS, 1/3 AVDD, 2/3 AVDD and AVDD) This module uses an external resistor ladder to generate the LCD bias voltages. The external resistor ladder should be connected to the Bias 1 pin, Bias 2 pin, Bias 3 pin and VSS. The Bias 3 pin should also be connected to AVDD.
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PIC18F6390/6490/8390/8490 22.6 Pixel Control 22.8 The LCDDATAx registers contain bits which define the state of each pixel. Each bit defines one unique pixel. LCD Waveform Generation Table 22-2 shows the correlation of each bit in the LCDDATAx registers to the respective common and segment signals. LCD waveform generation is based on the philosophy that the net AC voltage across the dark pixel should be maximized and the net AC voltage across the clear pixel should be minimized.
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PIC18F6390/6490/8390/8490 FIGURE 22-4: TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE V1 COM0 V0 COM0 V1 SEG0 V0 V1 SEG1 SEG0 SEG2 SEG7 SEG6 SEG5 SEG4 SEG3 SEG1 V0 V1 V0 COM0-SEG0 -V1 COM0-SEG1 V0 1 Frame © 2007 Microchip Technology Inc.
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PIC18F6390/6490/8390/8490 FIGURE 22-5: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE V2 COM0 V1 V0 COM1 V2 COM0 COM1 V1 V0 V2 V1 SEG0 V0 SEG0 SEG1 SEG2 SEG3 V2 V1 SEG1 V0 V2 V1 V0 COM0-SEG0 -V1 -V2 V2 V1 V0 COM0-SEG1 -V1 -V2 1 Frame DS39629C-page 266 © 2007 Microchip Technology Inc.
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PIC18F6390/6490/8390/8490 FIGURE 22-6: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE V2 V1 COM0 COM1 V0 COM0 V2 COM1 V1 V0 V2 SEG0 V1 SEG0 SEG1 SEG2 SEG3 V0 V2 SEG1 V1 V0 V2 V1 V0 COM0-SEG0 -V1 -V2 V2 V1 V0 COM0-SEG1 -V1 -V2 2 Frames © 2007 Microchip Technology Inc.
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PIC18F6390/6490/8390/8490 FIGURE 22-7: TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE V3 V2 COM0 V1 COM1 V0 V3 COM0 V2 COM1 V1 V0 V3 V2 SEG0 V1 V0 SEG0 SEG1 SEG2 SEG3 V3 V2 SEG1 V1 V0 V3 V2 V1 V0 COM0-SEG0 -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 -V1 -V2 1 Frame DS39629C-page 268 -V3 © 2007 Microchip Technology Inc.
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PIC18F6390/6490/8390/8490 FIGURE 22-8: TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE V3 V2 COM0 V1 COM1 V0 V3 COM0 V2 COM1 V1 V0 V3 V2 SEG0 V1 V0 SEG0 SEG1 SEG2 SEG3 V3 V2 SEG1 V1 V0 V3 V2 V1 V0 COM0-SEG0 -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 -V1 -V2 2 Frames © 2007 Microchip Technology Inc.
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PIC18F6390/6490/8390/8490 FIGURE 22-9: TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE V2 COM0 V1 V0 COM2 V2 COM1 V1 V0 COM1 COM0 V2 COM2 V1 V0 V2 SEG0 SEG2 V1 SEG0 SEG1 SEG2 V0 V2 SEG1 V1 V0 V2 V1 V0 COM0-SEG0 -V1 -V2 V2 V1 V0 COM0-SEG1 -V1 -V2 1 Frame DS39629C-page 270 © 2007 Microchip Technology Inc.
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PIC18F6390/6490/8390/8490 FIGURE 22-10: TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE V2 COM0 V1 V0 COM2 V2 COM1 V1 COM1 V0 COM0 V2 COM2 V1 V0 V2 V1 V0 SEG0 SEG1 SEG2 SEG0 V2 SEG1 V1 V0 V2 V1 V0 COM0-SEG0 -V1 -V2 V2 V1 V0 COM0-SEG1 -V1 -V2 2 Frames © 2007 Microchip Technology Inc.
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PIC18F6390/6490/8390/8490 FIGURE 22-11: TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE V3 V2 COM0 V1 V0 V3 COM2 V2 COM1 V1 COM1 V0 COM0 V3 V2 COM2 V1 V0 V3 V2 V1 V0 SEG0 SEG1 SEG2 SEG0 SEG2 V3 V2 SEG1 V1 V0 V3 V2 V1 V0 COM0-SEG0 -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 -V1 -V2 -V3 1 Frame DS39629C-page 272 © 2007 Microchip Technology Inc.
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PIC18F6390/6490/8390/8490 FIGURE 22-12: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE V3 V2 COM0 V1 V0 V3 COM2 V2 COM1 V1 COM1 V0 COM0 V3 V2 COM2 V1 V0 V3 V2 V1 V0 SEG0 SEG1 SEG2 SEG0 V3 V2 SEG1 V1 V0 V3 V2 V1 V0 COM0-SEG0 -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 -V1 -V2 -V3 2 Frames © 2007 Microchip Technology Inc.
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PIC18F6390/6490/8390/8490 FIGURE 22-13: TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 V3 V2 V1 V0 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 COM3 V3 V2 V1 V0 SEG0 V3 V2 V1 V0 SEG1 V3 V2 V1 V0 COM0-SEG0 V3 V2 V1 V0 -V1 -V2 -V3 COM0-SEG1 V3 V2 V1 V0 -V1 -V2 -V3 SEG0 SEG1 COM0 1 Frame DS39629C-page 274 © 2007 Microchip Technology Inc.
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PIC18F6390/6490/8390/8490 FIGURE 22-14: TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 V3 V2 V1 V0 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 COM3 V3 V2 V1 V0 SEG0 V3 V2 V1 V0 SEG1 V3 V2 V1 V0 COM0-SEG0 V3 V2 V1 V0 -V1 -V2 -V3 COM0-SEG1 V3 V2 V1 V0 -V1 -V2 -V3 SEG0 SEG1 COM0 2 Frames © 2007 Microchip Technology Inc.
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PIC18F6390/6490/8390/8490 22.9 LCD Interrupts When the LCD driver is running with Type-B waveforms and the LMUX1:LMUX0 bits are not equal to ‘00’, there are some additional issues that must be addressed. Since the DC voltage on the pixel takes two frames to maintain zero volts, the pixel data must not change between subsequent frames.
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PIC18F6390/6490/8390/8490 22.10 Operation During Sleep The LCD module can operate during Sleep. The selection is controlled by bit, SLPEN (LCDCON<6>). Setting the SLPEN bit allows the LCD module to go to Sleep. Clearing the SLPEN bit allows the module to continue to operate during Sleep. If a SLEEP instruction is executed and SLPEN = 1, the LCD module will cease all functions and go into a very low-current consumption mode.
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PIC18F6390/6490/8390/8490 22.11 Configuring the LCD Module 4. The following is the sequence of steps to configure the LCD module. 5. 1. 2. 3. Select the frame clock prescale using bits, LP3:LP0 (LCDPS<3:0>). Configure the appropriate pins to function as segment drivers using the LCDSEx registers. Configure the LCD module for the following using the LCDCON register: - Multiplex and Bias mode, LMUX1:LMUX0 bits - Timing source, CS1:CS0 bits - Sleep mode, SLPEN bit DS39629C-page 278 6.
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PIC18F6390/6490/8390/8490 TABLE 22-6: Name REGISTERS ASSOCIATED WITH LCD OPERATION Bit 7 INTCON Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page INT0IE RBIE TMR0IF INT0IF RBIF 59 PIR3 — LCDIF RC2IF TX2IF — — — — 61 PIE3 — LCDIE RC2IE TX2IE — — — — 61 IPR3 — LCDIP RC2IP TX2IP — — — — 61 IPEN SBOREN — RI TO PD POR BOR 60 LCDDATA23(1) S47C3 S46C3 S45C3 S44C3 S43C3 S42C3 S41C3 S40C3 63 LCDDATA22(1) S39C3
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PIC18F6390/6490/8390/8490 23.0 SPECIAL FEATURES OF THE CPU A complete discussion of device Resets and interrupts is available in previous sections of this data sheet. In addition to their Power-up and Oscillator Start-up Timers provided for Resets, PIC18F6390/6490/8390/ 8490 devices have a Watchdog Timer, which is either permanently enabled via the Configuration bits, or software controlled (if configured as disabled).
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PIC18F6390/6490/8390/8490 REGISTER 23-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-0 R/P-0 U-0 U-0 R/P-0 R/P-1 R/P-1 R/P-1 IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7 IESO: Internal/External Oscillator Switchover bit 1 = Oscillator Switchover mode enabled 0 = Oscillator Switchover mode disabl
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PIC18F6390/6490/8390/8490 REGISTER 23-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — BORV1 BORV0 BOREN1(1) BOREN0(1) PWRTEN(1) bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7-5 Unimplemented: Read as ‘0’ bit 4-3 BORV1:BORV0: Brown-out Reset Voltage bits 11 = VBOR set to 2.
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PIC18F6390/6490/8390/8490 REGISTER 23-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS3:WDTPS0: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101
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PIC18F6390/6490/8390/8490 REGISTER 23-5: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 R/P-0 U-0 U-0 U-0 U-0 U-0 R/P-1 DEBUG XINST — — — — — STVREN bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background debug
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PIC18F6390/6490/8390/8490 REGISTER 23-7: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F6390/6490/8390/8490 DEVICES R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7-5 DEV2:DEV0: Device ID bits 100 = PIC18F8390/8490 101 = PIC18F6390/6490 bit 4-0 REV4:REV0: Revision ID bits These bits are used to indicate the dev
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PIC18F6390/6490/8390/8490 23.2 Watchdog Timer (WDT) For PIC18F6390/6490/8390/8490 devices, the WDT is driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexer, controlled by bits in Configuration Register 2H. Available periods range from 4 ms to 134.2 seconds (2.
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PIC18F6390/6490/8390/8490 REGISTER 23-9: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 Unimplemented: Read as ‘0’ bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note 1: This bit has no effect if the Configurat
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PIC18F6390/6490/8390/8490 23.3 Two-Speed Start-up Reset. For wake-ups from Sleep, the INTOSC or postscaler clock sources can be selected by setting the IRCF2:IRCF0 bits prior to entering Sleep mode. The Two-Speed Start-up feature helps to minimize the latency period from oscillator start-up to code execution by allowing the microcontroller to use the INTRC oscillator as a clock source until the primary clock source is available. It is enabled by setting the IESO Configuration bit.
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PIC18F6390/6490/8390/8490 23.4 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator block. The FSCM function is enabled by setting the FCMEN Configuration bit. When FSCM is enabled, the INTRC oscillator runs at all times to monitor clocks to peripherals and provide a backup clock in the event of a clock failure.
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PIC18F6390/6490/8390/8490 FIGURE 23-4: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure Device Clock Output CM Output (Q) Failure Detected OSCFIF CM Test Note: 23.4.3 CM Test CM Test The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. FSCM INTERRUPTS IN POWER-MANAGED MODES By entering a power-managed mode, the clock multiplexer selects the clock source selected by the OSCCON register.
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PIC18F6390/6490/8390/8490 23.5 Program Verification and Code Protection 23.5.1 The overall structure of the code protection on the PIC18F6390/6490/8390/8490 Flash devices differs from previous PIC18 devices. For all devices in the PIC18F6X90/8X90 family, the user program memory is made of a single block. Figure 23-5 shows the program memory organization for individual devices. Code protection for this block is controlled by a single bit, CP (CONFIG5L<0>).
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PIC18F6390/6490/8390/8490 23.6 ID Locations 23.8 In-Circuit Debugger Eight memory locations (200000h-200007h) are designated as ID locations, where the user can store checksum or other code identification numbers. These locations are readable during normal execution through the TBLRD instruction. During program/verify, these locations are readable and writable. The ID locations can be read when the device is code-protected.
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PIC18F6390/6490/8390/8490 24.0 INSTRUCTION SET SUMMARY PIC18FXX90 devices incorporate the standard set of seventy-five PIC18 core instructions, as well as an extended set of 8 new instructions for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. 24.
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PIC18F6390/6490/8390/8490 TABLE 24-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
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PIC18F6390/6490/8390/8490 FIGURE 24-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 OPCODE Example Instruction 8 7 d 0 a ADDWF MYREG, W, B f (FILE #) d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE 15 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destinatio
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PIC18F6390/6490/8390/8490 TABLE 24-2: PIC18FXXXX INSTRUCTION SET Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes BYTE-ORIENTED OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f, d, a f, d, a
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PIC18F6390/6490/8390/8490 TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG f, b, a f, b, a f, b, a f, b, a f, d, a Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None
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PIC18F6390/6490/8390/8490 TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add Literal and WREG AND Literal with WREG Inclusive OR Literal with WREG Move Literal (12-bit) 2nd word to FSR(f) 1st word Move Literal to BSR<3:0> Move Literal to WREG Multiply Literal with WREG Return with Literal in WREG Subt
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PIC18F6390/6490/8390/8490 24.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW Syntax: ADDWF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) + (f) → dest Status Affected: N, OV, C, DC, Z k Operands: 0 ≤ k ≤ 255 Operation: (W) + k → W Status Affected: N, OV, C, DC, Z Encoding: 0000 1111 kkkk kkkk Description: The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.
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PIC18F6390/6490/8390/8490 ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: ADDWFC Syntax: ANDLW Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] f {,d {,a}} Operation: (W) + (f) + (C) → dest Status Affected: N,OV, C, DC, Z Encoding: 0010 Description: 00da ffff Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected.
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PIC18F6390/6490/8390/8490 ANDWF AND W with f BC Branch if Carry Syntax: ANDWF Syntax: BC Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: -128 ≤ n ≤ 127 Operation: if Carry bit is ‘1’, (PC) + 2 + 2n → PC Status Affected: None f {,d {,a}} Operation: (W) .AND. (f) → dest Status Affected: N, Z Encoding: 0001 Description: Encoding: 01da ffff ffff 1110 Description: The contents of W are ANDed with register ‘f’. If ‘d’ is ‘0’, the result is stored in W.
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PIC18F6390/6490/8390/8490 BCF Bit Clear f BN Branch if Negative Syntax: BCF Syntax: BN Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operands: -128 ≤ n ≤ 127 Operation: if Negative bit is ‘1’, (PC) + 2 + 2n → PC Status Affected: None f, b {,a} Operation: 0 → f Status Affected: None Encoding: 1001 Description: Encoding: bbba ffff ffff 1110 Description: Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank.
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PIC18F6390/6490/8390/8490 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC Syntax: BNN n n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Carry bit is ‘0’, (PC) + 2 + 2n → PC Operation: if Negative bit is ‘0’, (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 Description: 0011 nnnn nnnn If the Carry bit is ‘0’, then the program will branch. Encoding: 1110 Description: The 2’s complement number ‘2n’ is added to the PC.
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PIC18F6390/6490/8390/8490 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV Syntax: BNZ n n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Overflow bit is ‘0’, (PC) + 2 + 2n → PC Operation: if Zero bit is ‘0’, (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 Description: 0101 nnnn nnnn If the Overflow bit is ‘0’, then the program will branch.
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PIC18F6390/6490/8390/8490 BRA Unconditional Branch BSF Bit Set f Syntax: BRA Syntax: BSF Operands: -1024 ≤ n ≤ 1023 Operands: Operation: (PC) + 2 + 2n → PC Status Affected: None 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operation: 1 → f Status Affected: None Encoding: n 1101 Description: 0nnn nnnn nnnn Add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n.
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PIC18F6390/6490/8390/8490 BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operands: 0 ≤ f ≤ 255 0≤b<7 a ∈ [0,1] Operation: skip if (f) = 0 Operation: skip if (f) = 1 Status Affected: None Status Affected: None Encoding: 1011 Description: bbba ffff ffff If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skipped.
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PIC18F6390/6490/8390/8490 BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV Operands: 0 ≤ f ≤ 255 0≤b<7 a ∈ [0,1] Operands: -128 ≤ n ≤ 127 Operation: if Overflow bit is ‘1’, (PC) + 2 + 2n → PC Status Affected: None Operation: (f) → f Status Affected: None Encoding: 0111 Description: Encoding: bbba ffff ffff 1110 Description: Bit ‘b’ in data memory location ‘f’ is inverted. 0100 nnnn nnnn If the Overflow bit is ‘1’, then the program will branch.
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PIC18F6390/6490/8390/8490 BZ Branch if Zero CALL Subroutine Call Syntax: BZ Syntax: CALL k {,s} n Operands: -128 ≤ n ≤ 127 Operands: Operation: if Zero bit is ‘1’, (PC) + 2 + 2n → PC 0 ≤ k ≤ 1048575 s ∈ [0,1] Operation: Status Affected: None (PC) + 4 → TOS, k → PC<20:1>; if s = 1, (W) → WS, (STATUS) → STATUSS, (BSR) → BSRS Status Affected: None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is ‘1’, then the program will branch.
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PIC18F6390/6490/8390/8490 CLRF Clear f Syntax: CLRF Operands: 0 ≤ f ≤ 255 a ∈ [0,1] f {,a} Operation: 000h → f, 1→Z Status Affected: Z Encoding: 0110 Description: 101a ffff ffff Clears the contents of the specified register.
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PIC18F6390/6490/8390/8490 COMF Complement f CPFSEQ Compare f with W, Skip if f = W Syntax: COMF Syntax: CPFSEQ Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) – (W), skip if (f) = (W) (unsigned comparison) Status Affected: None f {,d {,a}} 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: Operation: (f) → dest Status Affected: N, Z Encoding: 0001 Description: 11da ffff ffff The contents of register ‘f’ are complemented. If ‘d’ is ‘1’, the result is stored in W.
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PIC18F6390/6490/8390/8490 CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT Syntax: CPFSLT Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) − (W), skip if (f) > (W) (unsigned comparison) Operation: (f) – (W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: Description: 0110 f {,a} 010a ffff ffff Compares the contents of data memory location ‘f’ to the contents of t
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PIC18F6390/6490/8390/8490 DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: Operation: If [W<3:0> >9] or [DC = 1] then, (W<3:0>) + 6 → W<3:0>; else, (W<3:0>) → W<3:0>; 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest Status Affected: C, DC, N, OV, Z Encoding: If [W<7:4> >9] or [C = 1] then, (W<7:4>) + 6 → W<7:4>, C = 1; else, (W<7:4>) → W<7:4> Status Affected: 0000 Description: C Encoding: 0000 0000 0000 DAW adjus
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PIC18F6390/6490/8390/8490 DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest, skip if result = 0 Operation: (f) – 1 → dest, skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0010 Description: 11da ffff ffff The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W.
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PIC18F6390/6490/8390/8490 GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF Operands: 0 ≤ k ≤ 1048575 Operands: Operation: k → PC<20:1> Status Affected: None 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 1110 1111 2nd word(k<19:8>) 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 GOTO allows an unconditional branch Description: Encoding: 0010 Description: anywhere within entire 2-Mbyte memory range
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PIC18F6390/6490/8390/8490 INCFSZ Increment f, Skip if 0 INFSNZ Syntax: INCFSZ Syntax: INFSNZ 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] f {,d {,a}} Increment f, Skip if not 0 f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: Operation: (f) + 1 → dest, skip if result = 0 Operation: (f) + 1 → dest, skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0011 Description: 11da ffff ffff The contents of register ‘f’ are incremented.
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PIC18F6390/6490/8390/8490 IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF Operands: 0 ≤ k ≤ 255 Operands: Operation: (W) .OR. k → W Status Affected: N, Z 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .OR. (f) → dest Status Affected: N, Z Encoding: 0000 1001 kkkk kkkk Description: The contents of W are ORed with the eight-bit literal ‘k’. The result is placed in W.
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PIC18F6390/6490/8390/8490 LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF Operands: 0≤f≤2 0 ≤ k ≤ 4095 Operands: Operation: k → FSRf 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Status Affected: None Operation: f → dest Status Affected: N, Z Encoding: 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the file select register pointed to by ‘f’.
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PIC18F6390/6490/8390/8490 MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF fs,fd Syntax: MOVLW k Operands: 0 ≤ fs ≤ 4095 0 ≤ fd ≤ 4095 Operands: 0 ≤ k ≤ 255 Operation: k → BSR None Operation: (fs) → fd Status Affected: Status Affected: None Encoding: Encoding: 1st word (source) 1100 1111 2nd word (destin.) Description: ffff ffff ffffs ffffd ffff ffff The contents of source register ‘fs’ are moved to destination register ‘fd’.
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PIC18F6390/6490/8390/8490 MOVLW Move Literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF Operands: 0 ≤ k ≤ 255 Operands: Operation: k→W 0 ≤ f ≤ 255 a ∈ [0,1] Status Affected: None Encoding: 0000 Description: 1110 kkkk kkkk The eight-bit literal ‘k’ is loaded into W.
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PIC18F6390/6490/8390/8490 MULLW Multiply Literal with W MULWF Multiply W with f Syntax: MULLW Syntax: MULWF Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (W) x (f) → PRODH:PRODL Status Affected: None k Operands: 0 ≤ k ≤ 255 Operation: (W) x k → PRODH:PRODL Status Affected: None Encoding: 0000 Description: 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in the PRODH:PRODL register pair.
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PIC18F6390/6490/8390/8490 NEGF Negate f NOP No Operation Syntax: NEGF Syntax: NOP Operands: 0 ≤ f ≤ 255 a ∈ [0,1] f {,a} Operands: None Operation: No operation None Operation: (f) + 1 → f Status Affected: Status Affected: N, OV, C, DC, Z Encoding: Encoding: 0110 Description: 110a ffff Location ‘f’ is negated using two’s complement. The result is placed in the data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank.
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PIC18F6390/6490/8390/8490 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) → bit bucket Operation: (PC + 2) → TOS Status Affected: None Status Affected: None Encoding: 0000 Description: 0000 0000 0110 The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.
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PIC18F6390/6490/8390/8490 RCALL Relative Call RESET Reset Syntax: RCALL Syntax: RESET n Operands: -1024 ≤ n ≤ 1023 Operands: None Operation: (PC) + 2 → TOS, (PC) + 2 + 2n → PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 Description: 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack.
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PIC18F6390/6490/8390/8490 RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (TOS) → PC, 1 → GIE/GIEH or PEIE/GIEL; if s = 1, (WS) → W, (STATUSS) → STATUS, (BSRS) → BSR, PCLATU, PCLATH are unchanged Operation: k → W, (TOS) → PC, PCLATU, PCLATH are unchanged Status Affected: None Status Affected: 0000 0000 Description: 0000 0001 Words: 1 Cycles: 2 Q Cycle Activity: kkkk kkkk W is loaded
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PIC18F6390/6490/8390/8490 RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF Operands: s ∈ [0,1] Operands: Operation: (TOS) → PC; if s = 1, (WS) → W, (STATUSS) → STATUS, (BSRS) → BSR, PCLATU, PCLATH are unchanged 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<7>) → C, (C) → dest<0> Status Affected: C, N, Z Status Affected: None Encoding: 0000 Description: Encoding: 0000 0001 001s 0011 Description: Return from subrou
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PIC18F6390/6490/8390/8490 RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry Syntax: RLNCF Syntax: RRCF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<7>) → dest<0> Operation: Status Affected: N, Z (f) → dest, (f<0>) → C, (C) → dest<7> Status Affected: C, N, Z Encoding: 0100 Description: f {,d {,a}} 01da ffff ffff The contents of register ‘f’ are rotated one bit to the left.
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PIC18F6390/6490/8390/8490 RRNCF Rotate Right f (No Carry) SETF Syntax: RRNCF Syntax: SETF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: FFh → f Operation: (f) → dest, (f<0>) → dest<7> Status Affected: None Status Affected: Encoding: N, Z Encoding: 0100 Description: f {,d {,a}} 00da Set f ffff ffff 0110 Description: The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W.
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PIC18F6390/6490/8390/8490 SLEEP Enter Sleep mode SUBFWB Subtract f from W with Borrow Syntax: SLEEP Syntax: SUBFWB Operands: None Operands: Operation: 00h → WDT, 0 → WDT postscaler, 1 → TO, 0 → PD 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) – (f) – (C) → dest Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0000 Encoding: 0000 0000 0011 0101 Description: The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set.
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PIC18F6390/6490/8390/8490 SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF Operands: 0 ≤ k ≤ 255 Operands: Operation: k – (W) → W Status Affected: N, OV, C, DC, Z 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) → dest Status Affected: N, OV, C, DC, Z Encoding: 0000 1000 kkkk kkkk Description: W is subtracted from the eight-bit literal ‘k’. The result is placed in W.
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PIC18F6390/6490/8390/8490 SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB Syntax: SWAPF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) – (C) → dest Operation: (f<3:0>) → dest<7:4>, Status Affected: N, OV, C, DC, Z Encoding: 0101 Description: f {,d {,a}} 10da (f<7:4>) → dest<3:0> ffff ffff Subtract W and the Carry flag (borrow) from register ‘f’ (2’s complement method).
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PIC18F6390/6490/8390/8490 TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) → TABLAT, TBLPTR – No Change; if TBLRD *+, (Prog Mem (TBLPTR)) → TABLAT, (TBLPTR) + 1 → TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) → TABLAT, (TBLPTR) – 1 → TBLPTR; if TBLRD +*, (TBLPTR) + 1 → TBLPTR, (Prog Mem (TBLPTR)) → TABLAT Status Affected: None Encoding: Description: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *=3 +* B
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PIC18F6390/6490/8390/8490 TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+; Operands: None Operation: if TBLWT*, (TABLAT) → Holding Register, TBLPTR – No Change; if TBLWT*+, (TABLAT) → Holding Register, (TBLPTR) + 1 → TBLPTR; if TBLWT*-, (TABLAT) → Holding Register, (TBLPTR) – 1 → TBLPTR; if TBLWT+*, (TBLPTR) + 1 → TBLPTR, Before Instruction TABLAT = 55h TBLPTR = 00A356h HOLDING REGISTER (00A356h) = FFh After Instructions (table write completion)
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PIC18F6390/6490/8390/8490 TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → W N, Z Operation: skip if f = 0 Status Affected: Status Affected: None Encoding: Encoding: 0110 Description: 011a ffff ffff If ‘f’ = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction.
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PIC18F6390/6490/8390/8490 XORWF Exclusive OR W with f Syntax: XORWF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .XOR. (f) → dest Status Affected: N, Z Encoding: 0001 Description: f {,d {,a}} 10da ffff ffff Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank.
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PIC18F6390/6490/8390/8490 24.2 Extended Instruction Set A summary of the instructions in the extended instruction set is provided in Table 24-3. Detailed descriptions are provided in Section 24.2.2 “Extended Instruction Set”. The opcode field descriptions in Table 24-1 apply to both the standard and extended PIC18 instruction sets. In addition to the standard 75 instructions of the PIC18 instruction set, PIC18FXX90 devices also provide an optional extension to the core CPU functionality.
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PIC18F6390/6490/8390/8490 24.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operands: 0 ≤ k ≤ 63 FSR(f) + k → FSR(f) Operation: Operation: FSR2 + k → FSR2, PC = (TOS) Status Affected: None Status Affected: None Encoding: 1110 1000 ffkk kkkk Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’.
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PIC18F6390/6490/8390/8490 CALLW Subroutine Call Using WREG MOVSF Syntax: CALLW Syntax: MOVSF [zs], fd Operands: None Operands: Operation: (PC + 2) → TOS, (W) → PCL, (PCLATH) → PCH, (PCLATU) → PCU 0 ≤ zs ≤ 127 0 ≤ fd ≤ 4095 Operation: ((FSR2) + zs) → fd Status Affected: None Status Affected: 0000 Description Encoding: None Encoding: 0000 Move Indexed to f 0001 0100 First, the return address (PC + 2) is pushed onto the return stack.
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PIC18F6390/6490/8390/8490 MOVSS Move Indexed to Indexed PUSHL Syntax: Syntax: PUSHL k Operands: MOVSS [zs], [zd] 0 ≤ zs ≤ 127 0 ≤ zd ≤ 127 Operands: 0 ≤ k ≤ 255 Operation: ((FSR2) + zs) → ((FSR2) + zd) Operation: k → (FSR2), FSR2 – 1→ FSR2 Status Affected: None Status Affected: None Encoding: 1st word (source) 1110 1111 2nd word (dest.) Description 1011 xxxx 1zzz xzzz zzzzs zzzzd The contents of the source register are moved to the destination register.
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PIC18F6390/6490/8390/8490 SUBFSR Subtract Literal from FSR SUBULNK Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operands: 0 ≤ k ≤ 63 Operation: Operation: FSRf – k → FSRf FSR2 – k → FSR2, (TOS) → PC Status Affected: None Encoding: 1110 Subtract Literal from FSR2 and Return Status Affected: None 1001 ffkk kkkk Description: The 6-bit literal ‘k’ is subtracted from the contents of the FSR specified by ‘f’.
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PIC18F6390/6490/8390/8490 24.2.3 Note: BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing mode (Section 5.6.1 “Indexed Addressing With Literal Offset”).
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PIC18F6390/6490/8390/8490 ADDWF ADD W to Indexed (Indexed Literal Offset mode) BSF Bit Set Indexed (Indexed Literal Offset mode) Syntax: ADDWF Syntax: BSF [k], b Operands: 0 ≤ k ≤ 95 d ∈ [0,1] a=0 Operands: 0 ≤ f ≤ 95 0≤b≤7 a=0 Operation: (W) + ((FSR2) + k) → dest Operation: 1 → ((FSR2 + k)) Status Affected: None [k] {,d} Status Affected: N, OV, C, DC, Z Encoding: 0010 Description: 01d0 kkkk kkkk The contents of W are added to the contents of the register indicated by FSR2, offse
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PIC18F6390/6490/8390/8490 24.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB® IDE TOOLS The latest versions of Microchip’s software tools have been designed to fully support the extended instruction set of the PIC18FXX90 family of devices. This includes the MPLAB C18 C compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device.
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PIC18FXX90 25.
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PIC18FXX90 25.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.
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PIC18FXX90 25.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
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PIC18FXX90 25.11 PICSTART Plus Development Programmer 25.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins.
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PIC18F6390/6490/8390/8490 26.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD and MCLR) .............................................
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PIC18F6390/6490/8390/8490 FIGURE 26-1: PIC18F6390/6490/8390/8490 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18FX390/X490 Voltage 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz Frequency FIGURE 26-2: PIC18LF6390/6490/8390/8490 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V PIC18LFX390/X490 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz 4 MHz Frequency FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.
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PIC18F6390/6490/8390/8490 26.1 DC Characteristics: Supply Voltage PIC18F6390/6490/8390/8490 (Industrial) PIC18LF6390/6490/8390/8490 (Industrial) PIC18LF6390/6490/8390/8490 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F6390/6490/8390/8490 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No.
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PIC18F6390/6490/8390/8490 26.2 DC Characteristics: Power-Down and Supply Current PIC18F6390/6490/8390/8490 (Industrial) PIC18LF6390/6490/8390/8490 (Industrial) PIC18LF6390/6490/8390/8490 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F6390/6490/8390/8490 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No.
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PIC18F6390/6490/8390/8490 26.2 DC Characteristics: Power-Down and Supply Current PIC18F6390/6490/8390/8490 (Industrial) PIC18LF6390/6490/8390/8490 (Industrial) (Continued) PIC18LF6390/6490/8390/8490 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F6390/6490/8390/8490 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No.
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PIC18F6390/6490/8390/8490 26.2 DC Characteristics: Power-Down and Supply Current PIC18F6390/6490/8390/8490 (Industrial) PIC18LF6390/6490/8390/8490 (Industrial) (Continued) PIC18LF6390/6490/8390/8490 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F6390/6490/8390/8490 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No.
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PIC18F6390/6490/8390/8490 26.2 DC Characteristics: Power-Down and Supply Current PIC18F6390/6490/8390/8490 (Industrial) PIC18LF6390/6490/8390/8490 (Industrial) (Continued) PIC18LF6390/6490/8390/8490 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F6390/6490/8390/8490 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No.
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PIC18F6390/6490/8390/8490 26.2 DC Characteristics: Power-Down and Supply Current PIC18F6390/6490/8390/8490 (Industrial) PIC18LF6390/6490/8390/8490 (Industrial) (Continued) PIC18LF6390/6490/8390/8490 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F6390/6490/8390/8490 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No.
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PIC18F6390/6490/8390/8490 26.2 DC Characteristics: Power-Down and Supply Current PIC18F6390/6490/8390/8490 (Industrial) PIC18LF6390/6490/8390/8490 (Industrial) (Continued) PIC18LF6390/6490/8390/8490 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F6390/6490/8390/8490 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No.
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PIC18F6390/6490/8390/8490 26.2 DC Characteristics: Power-Down and Supply Current PIC18F6390/6490/8390/8490 (Industrial) PIC18LF6390/6490/8390/8490 (Industrial) (Continued) PIC18LF6390/6490/8390/8490 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F6390/6490/8390/8490 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No.
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PIC18F6390/6490/8390/8490 26.2 DC Characteristics: Power-Down and Supply Current PIC18F6390/6490/8390/8490 (Industrial) PIC18LF6390/6490/8390/8490 (Industrial) (Continued) PIC18LF6390/6490/8390/8490 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F6390/6490/8390/8490 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No.
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PIC18F6390/6490/8390/8490 26.2 DC Characteristics: Power-Down and Supply Current PIC18F6390/6490/8390/8490 (Industrial) PIC18LF6390/6490/8390/8490 (Industrial) (Continued) PIC18LF6390/6490/8390/8490 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F6390/6490/8390/8490 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No.
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PIC18F6390/6490/8390/8490 26.2 DC Characteristics: Power-Down and Supply Current PIC18F6390/6490/8390/8490 (Industrial) PIC18LF6390/6490/8390/8490 (Industrial) (Continued) PIC18LF6390/6490/8390/8490 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F6390/6490/8390/8490 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No.
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PIC18F6390/6490/8390/8490 26.3 DC Characteristics: PIC18F6390/6490/8390/8490 (Industrial) PIC18LF6390/6490/8390/8490 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Max Units Conditions VSS 0.15 VDD V VDD < 4.5V — 0.8 V 4.5V ≤ VDD ≤ 5.5V VSS VSS 0.2 VDD 0.
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PIC18F6390/6490/8390/8490 26.3 DC Characteristics: PIC18F6390/6490/8390/8490 (Industrial) PIC18LF6390/6490/8390/8490 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial DC CHARACTERISTICS Param Symbol No. VOL Characteristic Min Max Units Conditions Output Low Voltage D080 I/O Ports — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C D083 OSC2/CLKO (RC, RCIO, EC, ECIO modes) — 0.6 V IOL = 1.6 mA, VDD = 4.
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PIC18F6390/6490/8390/8490 TABLE 26-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial DC Characteristics Param No. Sym Characteristic Min Typ† Max Units Conditions 10.0 — 12.0 V — — 1 mA — 1K — E/W -40°C to +85°C VMIN — 5.
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PIC18F6390/6490/8390/8490 TABLE 26-2: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +85°C, unless otherwise stated. Param No. Sym Characteristics Min Typ Max Units Comments D300 VIOFF Input Offset Voltage — ±5.0 ±10 mV D301 VICM Input Common Mode Voltage* 0 — VDD – 1.5 V D302 CMRR Common Mode Rejection Ratio* 55 — — dB 300 TRESP Response Time*(1) — 150 400 ns PIC18FXXXX — 150 600 ns PIC18LFXXXX, VDD = 2.
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PIC18F6390/6490/8390/8490 FIGURE 26-3: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS For VDIRMAG = 1: VDD VHLVD (HLVDIF set by hardware) (HLVDIF can be cleared in software) VHLVD For VDIRMAG = 0: VDD HLVDIF TABLE 26-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Sym No.
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PIC18F6390/6490/8390/8490 26.4 26.4.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
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PIC18F6390/6490/8390/8490 26.4.2 TIMING CONDITIONS Note: The temperature and voltages specified in Table 26-5 apply to all timing specifications unless otherwise noted. Figure 26-4 specifies the load conditions for the timing specifications. TABLE 26-5: Because of space limitations, the generic terms “PIC18FXXXX” and “PIC18LFXXXX” are used throughout this section to refer to the PIC18F6390/6490/8390/8490 and PIC18LF6390/6490/8390/8490 families of devices specifically and only those devices.
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PIC18F6390/6490/8390/8490 26.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 26-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 26-6: Param. No. 1A EXTERNAL CLOCK TIMING REQUIREMENTS Symbol FOSC Characteristic Min External CLKI Frequency(1) DC 1 MHz XT, RC Oscillator mode DC 20 MHz HS Oscillator mode DC 31.25 kHz LP Oscillator mode DC 4 MHz RC Oscillator mode 0.
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PIC18F6390/6490/8390/8490 TABLE 26-7: Param No. PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V) Sym Characteristic Min Typ† Max 4 16 — — 10 40 Units F10 F11 FOSC Oscillator Frequency Range FSYS On-Chip VCO System Frequency F12 trc PLL Start-up Time (Lock Time) — — 2 ms ΔCLK CLKO Stability (Jitter) -2 — +2 % F13 Conditions MHz HS mode only MHz HS mode only † Data in “Typ” column is at 5V, 25°C, unless otherwise stated.
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PIC18F6390/6490/8390/8490 FIGURE 26-6: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 14 19 12 18 16 I/O pin (Input) 15 17 I/O pin (Output) Note: 20, 21 Refer to Figure 26-4 for load conditions. TABLE 26-9: Param No.
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PIC18F6390/6490/8390/8490 FIGURE 26-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 Oscillator Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure 26-4 for load conditions. FIGURE 26-8: BROWN-OUT RESET TIMING BVDD VDD 35 VBGAP = 1.
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PIC18F6390/6490/8390/8490 FIGURE 26-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1OSO/T13CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 26-4 for load conditions. TABLE 26-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Symbol Characteristic 40 TT0H T0CKI High Pulse Width No Prescaler 41 TT0L T0CKI Low Pulse Width No Prescaler 42 TT0P T0CKI Period No Prescaler With Prescaler With Prescaler 45 TT1H — ns 10 — ns 0.
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PIC18F6390/6490/8390/8490 FIGURE 26-10: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 Note: 54 Refer to Figure 26-4 for load conditions. TABLE 26-12: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param Symbol No. 50 51 TCCL TCCH Characteristic Min Max Units CCPx Input Low No Prescaler Time With PIC18FXXXX Prescaler PIC18LFXXXX 0.5 TCY + 20 — ns 10 — ns 20 — ns CCPx Input High Time 0.
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PIC18F6390/6490/8390/8490 FIGURE 26-11: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 bit 6 - - - - - - 1 MSb SDO LSb 75, 76 SDI MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure 26-4 for load conditions. TABLE 26-13: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param No. Symbol Characteristic Min Max Units 70 TSSL2SCH, TSSL2SCL SS ↓ to SCK ↓ or SCK ↑ Input 71 TSCH SCK Input High Time (Slave mode) Continuous 1.
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PIC18F6390/6490/8390/8490 FIGURE 26-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 MSb SDO bit 6 - - - - - - 1 LSb bit 6 - - - - 1 LSb In 75, 76 SDI MSb In 74 Note: Refer to Figure 26-4 for load conditions. TABLE 26-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No.
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PIC18F6390/6490/8390/8490 FIGURE 26-13: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - - 1 LSb 75, 76 MSb In SDI 77 bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure 26-4 for load conditions. TABLE 26-15: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param No.
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PIC18F6390/6490/8390/8490 FIGURE 26-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - - 1 LSb 75, 76 SDI MSb In Note: 77 bit 6 - - - - 1 LSb In 74 Refer to Figure 26-4 for load conditions. TABLE 26-16: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No.
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PIC18F6390/6490/8390/8490 FIGURE 26-15: I2C™ BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA Stop Condition Start Condition Note: Refer to Figure 26-4 for load conditions. TABLE 26-17: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No.
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PIC18F6390/6490/8390/8490 TABLE 26-18: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. No. 100 Symbol THIGH 101 TLOW 102 TR 103 TF TSU:STA 90 Characteristic Clock High Time Clock Low Time SDA and SCL Rise Time SDA and SCL Fall Time Min Max Units Conditions 100 kHz mode 4.0 — μs PIC18FXXXX must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — μs PIC18FXXXX must operate at a minimum of 10 MHz MSSP module 1.5 TCY — 100 kHz mode 4.
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PIC18F6390/6490/8390/8490 FIGURE 26-17: MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS SCL 93 91 90 92 SDA Stop Condition Start Condition Note: Refer to Figure 26-4 for load conditions. TABLE 26-19: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol No.
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PIC18F6390/6490/8390/8490 TABLE 26-20: MASTER SSP I2C™ BUS DATA REQUIREMENTS Param. Symbol No.
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PIC18F6390/6490/8390/8490 FIGURE 26-19: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX1/CK1 pin 121 121 RC7/RX1/DT1 pin 120 Note: 122 Refer to Figure 26-4 for load conditions. TABLE 26-21: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No.
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PIC18F6390/6490/8390/8490 TABLE 26-23: A/D CONVERTER CHARACTERISTICS: PIC18F6390/6490/8390/8490 (INDUSTRIAL) PIC18LF6390/6490/8390/8490 (INDUSTRIAL) Param Symbol No. Characteristic Min Typ Max Units ΔVREF ≥ 3.0V A01 NR Resolution — — 10 A03 EIL Integral Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A04 EDL Differential Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A06 EOFF Offset Error — — <±1 LSb ΔVREF ≥ 3.0V A07 EGN Gain Error — — <±1 LSb ΔVREF ≥ 3.
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PIC18F6390/6490/8390/8490 FIGURE 26-21: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 132 A/D CLK 9 A/D DATA 8 7 ... ... 2 1 0 NEW_DATA OLD_DATA ADRES TCY ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
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PIC18F6390/6490/8390/8490 27.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs and tables are not available at this time. © 2007 Microchip Technology Inc.
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PIC18F6390/6490/8390/8490 28.0 PACKAGING INFORMATION 28.1 Package Marking Information 64-Lead TQFP Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC18F6490 -I/PT e3 0710017 Example 80-Lead TQFP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
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PIC18F6390/6490/8390/8490 28.2 Package Details The following sections give the technical details of the packages.
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PIC18F6390/6490/8390/8490 /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ © 2007 Microchip Technology Inc.
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PIC18F6390/6490/8390/8490 APPENDIX A: REVISION HISTORY Revision A (July 2004) Original data sheet for PIC18F6390/6490/8390/8490 devices. APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1. Revision B (August 2004) Updated preliminary “electrical characteristics” data. Revision C (November 2007) Revised I2C™ Slave Mode Timing figure. Updated DC Power-Down and Supply Current table and package drawings.
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PIC18F6390/6490/8390/8490 APPENDIX C: CONVERSION CONSIDERATIONS This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC16C74A to a PIC16C74B.
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PIC18F6390/6490/8390/8490 APPENDIX E: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN716, “Migrating Designs from PIC16C74A/74B to PIC18C442.” The changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations.
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PIC18F6390/6490/8390/8490 INDEX A A/D ................................................................................... 231 A/D Converter Interrupt, Configuring ....................... 235 Acquisition Requirements ........................................ 236 ADCON0 Register .................................................... 231 ADCON1 Register .................................................... 231 ADCON2 Register .................................................... 231 ADRESH Register ................
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PIC18F6390/6490/8390/8490 Timer0 in 8-Bit Mode ................................................ 132 Timer1 ...................................................................... 136 Timer1 (16-Bit Read/Write Mode) ............................ 136 Timer2 ...................................................................... 142 Timer3 ...................................................................... 144 Timer3 (16-Bit Read/Write Mode) ............................
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PIC18F6390/6490/8390/8490 Data Memory ..................................................................... 71 Access Bank .............................................................. 73 and the Extended Instruction Set ............................... 84 Bank Select Register (BSR) ....................................... 71 General Purpose Registers ........................................ 73 Map for PIC18F6X90/8X90 Devices .......................... 72 Special Function Registers ..........................
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PIC18F6390/6490/8390/8490 Effect of a Reset ...................................................... 191 General Call Address Support ................................. 180 I2C Clock Rate w/BRG ............................................. 183 Master Mode ............................................................ 181 Operation ......................................................... 182 Reception ......................................................... 187 Repeated Start Condition Timing ..................
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PIC18F6390/6490/8390/8490 Interrupt Sources ............................................................. 281 A/D Conversion Complete ....................................... 235 Capture Complete (CCP) ......................................... 150 Compare Complete (CCP) ....................................... 151 Interrupt-on-Change (RB7:RB4) .............................. 112 INTx Pin ................................................................... 108 PORTB, Interrupt-on-Change .........................
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PIC18F6390/6490/8390/8490 RA1/AN1 .............................................................. 13, 21 RA2/AN2/VREF-/SEG16 ....................................... 13, 21 RA3/AN3/VREF+/SEG17 ...................................... 13, 21 RA4/T0CKI/SEG14 .............................................. 13, 21 RA5/AN4/HLVDIN/SEG15 ................................... 13, 21 RB0/INT0 ............................................................. 14, 22 RB1/INT1/SEG8 .................................................
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PIC18F6390/6490/8390/8490 Power-Managed Modes ..................................................... 41 and Multiple Sleep Commands .................................. 42 Effects on Clock Sources ........................................... 39 Entering ...................................................................... 41 Exiting Idle and Sleep Modes by Reset ............................................................. 48 by WDT Time-out ...............................................
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PIC18F6390/6490/8390/8490 Reset .................................................................................. 51 MCLR Reset, during Power-Managed Modes ........... 51 MCLR Reset, Normal Operation ................................ 51 Power-on Reset (POR) .............................................. 51 Programmable Brown-out Reset (BOR) .................... 51 Stack Full Reset ......................................................... 51 Stack Underflow Reset .............................................
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PIC18F6390/6490/8390/8490 BRG Reset Due to SDA Arbitration During Start Condition ..................................... 193 Brown-out Reset (BOR) ........................................... 372 Bus Collision During a Repeated Start Condition (Case 1) .................................. 194 Bus Collision During a Repeated Start Condition (Case 2) .................................. 194 Bus Collision During a Start Condition (SCL = 0) .........................................
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PIC18F6390/6490/8390/8490 Top-of-Stack Access .......................................................... 66 TSTFSZ ............................................................................ 335 Two-Speed Start-up ................................................. 281, 289 Two-Word Instructions Example Cases .......................................................... 70 TXSTA1 Register BRGH Bit ................................................................. 201 TXSTA2 Register BRGH Bit ....................
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PIC18FXX90 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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PIC18FXX90 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
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PIC18F6390/6490/8390/8490 PIC18F6390/6490/8390/8490 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device(1), (2) PIC18F6390/6490/8390/8490, PIC18F6390/6490/8390/8490T; VDD range 4.2V to 5.5V PIC18LF6390/6490/8390/8490, PIC18LF6390/6490/8390/8490T; VDD range 2.0V to 5.
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