Datasheet

 2009-2011 Microchip Technology Inc. DS39957D-page 99
PIC18F87K90 FAMILY
F50h CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx
F51h ECCP2DEL P2RSEN P2DC6 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000
F52h ECCP2AS ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000
F53h PADCFG1 RDPU REPU RJPU
(2)
— — RTSECSEL1 RTSECSEL0 — 000- -00-
F54h CM1CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 0001 1111
F55h CTMUICON ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG1 0000 0000
F56h CTMUCONL EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT 0000 0000
F57h CTMUCONH CTMUEN
— CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 0-00 0000
F58h ALRMVALL Alarm Value High Register Window based on APTR<1:0> 0000 0000
F59h ALRMVALH Alarm Value High Register Window based on APTR<1:0> xxxx xxxx
F5Ah ALRMRPT ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 0000 0000
F5Bh ALRMCFG ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 0000 0000
F5Ch RTCVALL RTCC Value Low Register Window based on RTCPTR<1:0> 0000 0000
F5Dh RTCVALH RTCC Value High Register Window based on RTCPTR<1:0> xxxx xxxx
F5Eh RTCCAL CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 xxxx xxxx
F5Fh RTCCFG RTCEN
— RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 0-00 0000
F60h PIE6
— — —EEIE— CMP3IE CMP2IE CMP1IE ---0 -000
F61h EEDATA EEPROM Data Register 0000 0000
F62h EEADR EEPROM Address Register Low Byte 0000 0000
F63h EEADRH EEPROM Address Register High Byte ---- --00
F64h OSCCON2
— SOSCRUN — —SOSCGO— MFIOFS MFIOSEL -0-- 0-x0
F65h BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16
— WUE ABDEN 0000 0-x0
F66h LCDDATA0 S07C0 S06C0 S05C0 S04C0 S03C0 S02C0 S01C0 S00C0 xxxx xxxx
F67h LCDDATA1 S15C0 S14C0 S13C0 S12C0 S11C0 S10C0 S09C0 S08C0 xxxx xxxx
F68h LCDDATA2 S23C0 S22C0 S21C0 S20C0 S19C0 S18C0 S17C0 S16C0 xxxx xxxx
F69h LCDDATA3 S31C0 S30C0 S29C0 S28C0 S27C0 S26C0 S25C0 S24C0 xxxx xxxx
F6Ah LCDDATA4 S39C0 S38C0 S37C0 S36C0 S35C0 S34C0 S33C0 S32C0 xxxx xxxx
F6Bh LCDDATA5 S47C0 S46C0 S45C0 S44C0 S43C0 S42C0 S41C0 S40C0 xxxx xxxx
F6Ch LCDDATA6 S07C1 S06C1 S05C1 S04C1 S03C1 S02C1 S01C1 S00C1 xxxx xxxx
F6Dh LCDDATA7 S15C1 S14C1 S13C1 S12C1 S11C1 S10C1 S09C1 S08C1 xxxx xxxx
F6Eh LCDDATA8 S23C1 S22C1 S21C1 S20C1 S19C1 S18C1 S17C1 S16C1 xxxxxxxx
F6Fh LCDDATA9 S31C1 S30C1 S29C1 S28C1 S27C1 S26C1 S25C1 S24C1 xxxx xxxx
F70h LCDDATA10
(2)
S39C1
(2)
S38C1
(2)
S37C1
(2)
S36C1
(2)
S35C1
(2)
S34C1
(2)
S33C1
(2)
S32C1 xxxx xxxx
F71h LCDDATA11
(2)
S47C1 S46C1 S45C1 S44C1 S43C1 S42C1 S41C1 S40C1 xxxx xxxx
F72h LCDDATA12 S07C2 S06C2 S05C2 S04C2 S03C2 S02C2 S01C2 S00C2 xxxx xxxx
F73h LCDDATA13 S15C2 S14C2 S13C2 S12C2 S11C2 S10C2 S09C2 S08C2 xxxx xxxx
F74h LCDDATA14 S23C2 S22C2 S21C2 S20C2 S19C2 S18C2 S17C2 S16C2 xxxx xxxx
F75h LCDDATA15 S31C2 S30C2 S29C2 S28C2 S27C2 S26C2 S25C2 S24C2 xxxx xxxx
F76h LCDDATA16
(2)
S39C2
(2)
S38C2
(2)
S37C2
(2)
S36C2
(2)
S35C2
(2)
S34C2
(2)
S33C2
(2)
S32C2 xxxx xxxx
F77h LCDDATA17
(2)
S47C2 S46C2 S45C2 S44C2 S43C2 S42C2 S41C2 S40C2 xxxx xxxx
F78h LCDDATA18 S07C3 S06C3 S05C3 S04C3 S03C3 S02C3 S01C3 S00C3 xxxx xxxx
F79h LCDDATA19 S15C3 S14C3 S13C3 S12C3 S11C3 S10C3 S09C3 S08C3 xxxx xxxx
F7Ah LCDDATA20 S23C3 S22C3 S21C3 S20C3 S19C3 S18C3 S17C3 S16C3 xxxx xxxx
F7Bh LCDDATA21 S31C3 S30C3 S29C3 S28C3 S27C3 S26C3 S25C3 S24C3 xxxx xxxx
F7Ch LCDDATA22 S39C3
(2)
S38C3
(2)
S37C3
(2)
S36C3
(2)
S35C3
(2)
S34C3
(2)
S33C3
(2)
S32C3 xxxx xxxx
F7Dh LCDDATA23
(2)
S47C3 S46C3 S45C3 S44C3 S43C3 S42C3 S41C3 S40C3 xxxx xxxx
F7Eh EECON2 EEPROM Control Register 2 (not a physical register) ---- ----
F7Fh EECON1 EEPGD CFGS
— FREE WRERR WREN WR RD xx-0 x000
F80h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx
TABLE 6-2: PIC18F87K90 FAMILY REGISTER FILE SUMMARY (CONTINUED)
Address File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Note 1: This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.
2: Unimplemented in 64-pin devices (PIC18F6XK90).
3: Unimplemented in devices with a program memory of 32 Kbytes (PIC18FX5K90).