Datasheet

PIC18F87K90 FAMILY
DS39957D-page 558  2009-2011 Microchip Technology Inc.
Synchronous Slave Mode ......................................... 371
Associated Registers, Receive ......................... 372
Associated Registers, Transmit ........................ 371
Reception.......................................................... 372
Transmission..................................................... 371
Extended Instruction Set
ADDFSR ...................................................................494
ADDULNK................................................................. 494
CALLW......................................................................495
MOVSF .....................................................................495
MOVSS .....................................................................496
PUSHL ......................................................................496
SUBFSR ................................................................... 497
SUBULNK ................................................................. 497
External Oscillator Modes
Clock Input (EC, ECPLL Modes) ................................ 48
HS, HSPLL..................................................................46
F
Fail-Safe Clock Monitor............................................. 425, 445
Exiting Operation ...................................................... 445
Interrupts in Power-Managed Modes ........................ 446
POR or Wake from Sleep .........................................446
WDT During Oscillator Failure .................................. 445
Fast Register Stack............................................................. 89
Firmware Instructions........................................................451
Flash Program Memory..................................................... 111
Associated Registers ................................................119
Control Registers ......................................................112
EECON1, EECON2 ..........................................112
TABLAT (Table Latch) ...................................... 114
TBLPTR (Table Pointer) ................................... 114
Erasing......................................................................116
Sequence.......................................................... 116
Operation During Code-Protect ................................ 119
Protection Against Spurious Writes ..........................119
Reading..................................................................... 115
Table Pointer
Boundaries Based on Operation....................... 114
Table Pointer Boundaries ......................................... 114
Table Reads, Table Writes ....................................... 111
Writing
Unexpected Termination................................... 119
Verify.................................................................119
Writing To..................................................................117
Sequence.......................................................... 117
FSCM.
See Fail-Safe Clock Monitor.
G
GOTO................................................................................ 472
H
Hardware Multiplier ........................................................... 127
8 x 8 Multiplication Algorithms ..................................127
Operation ..................................................................127
Performance Comparison (table).............................. 127
High/Low-Voltage Detect .................................................. 401
Applications............................................................... 404
Associated Registers ................................................405
Current Consumption................................................ 403
Effects of a Reset......................................................405
Operation ..................................................................402
During Sleep ..................................................... 405
Setup ........................................................................ 403
Start-up Time............................................................ 403
Typical Low-Voltage Detect Application ................... 404
HLVD.
See High/Low-Voltage Detect.
I
I/O Ports............................................................................ 153
Open-Drain Outputs.................................................. 154
Output Pin Drive ....................................................... 153
Pin Capabilities......................................................... 153
Pull-up Configuration ................................................ 153
I
2
C Mode (MSSP)
Acknowledge Sequence Timing ............................... 342
Associated Registers................................................ 348
Baud Rate Generator ............................................... 335
Bus Collision
During a Repeated Start Condition................... 346
During a Stop Condition ................................... 347
Clock Arbitration ....................................................... 336
Clock Stretching........................................................ 328
10-Bit Slave Receive Mode (SEN = 1) ............. 328
10-Bit Slave Transmit Mode ............................. 328
7-Bit Slave Receive Mode (SEN = 1) ............... 328
7-Bit Slave Transmit Mode ............................... 328
Clock Synchronization and the CKP bit.................... 329
Effects of a Reset ..................................................... 343
General Call Address Support .................................. 332
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2
C Clock Rate w/BRG.............................................. 335
Master Mode............................................................. 333
Operation.......................................................... 334
Reception ......................................................... 339
Repeated Start Condition Timing ..................... 338
Start Condition Timing ...................................... 337
Transmission .................................................... 339
Multi-Master Communication, Bus Collision
and Arbitration .................................................. 343
Multi-Master Mode.................................................... 343
Operation.................................................................. 318
Read/Write
Bit Information (R/W Bit) ................ 318, 321
Registers .................................................................. 313
Serial Clock (SCLx) .................................................. 321
Slave Mode............................................................... 318
Address Masking Modes
5-Bit .......................................................... 319
7-Bit .......................................................... 320
Addressing........................................................ 318
Reception ......................................................... 321
Transmission .................................................... 321
Sleep Operation........................................................ 343
Stop Condition Timing .............................................. 342
ID Locations.............................................................. 425, 450
INCF ................................................................................. 472
INCFSZ............................................................................. 473
In-Circuit Debugger........................................................... 450
In-Circuit Serial Programming (ICSP)....................... 425, 450
Indexed Literal Offset Addressing
and Standard PIC18 Instructions.............................. 498
Indexed Literal Offset Mode.............................................. 498
Indirect Addressing ........................................................... 105
INFSNZ............................................................................. 473
Instruction Cycle ................................................................. 90
Clocking Scheme........................................................ 90
Flow/Pipelining............................................................ 90