Datasheet

PIC18F87K90 FAMILY
DS39957D-page 48  2009-2011 Microchip Technology Inc.
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 3-3 shows how the R/C combination is
connected.
FIGURE 3-3: RC OSCILLATOR MODE
The RCIO Oscillator mode (Figure 3-4) functions like
the RC mode, except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).
FIGURE 3-4: RCIO OSCILLATOR MODE
3.5.1 EXTERNAL CLOCK INPUT
(EC MODES)
The EC and ECPLL Oscillator modes require an
external clock source to be connected to the OSC1 pin.
There is no oscillator start-up time required after a
Power-on Reset or after an exit from Sleep mode.
In the EC Oscillator mode, the oscillator frequency,
divided by 4, is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 3-5 shows the pin connections for the EC
Oscillator mode.
FIGURE 3-5: EXTERNAL CLOCK
INPUT OPERATION
(EC CONFIGURATION)
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 3-6. In
this configuration, the divide-by-4 output on OSC2 is
not available. Current consumption in this configuration
will be somewhat higher than EC mode, as the internal
oscillator’s feedback circuitry will be enabled (in EC
mode, the feedback circuit is disabled).
FIGURE 3-6: EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
3.5.2 PLL FREQUENCY MULTIPLIER
A Phase Lock Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency
oscillator circuit, or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals, or users who require higher
clock speeds from an internal oscillator.
3.5.2.1 HSPLL and ECPLL Modes
The HSPLL and ECPLL modes provide the ability to
selectively run the device at four times the external
oscillating source to produce frequencies up to 64 MHz.
The PLL is enabled by setting the PLLEN bit
(OSCTUNE<6>) or the PLLCFG bit (CONFIG1H<4>).
The PLLEN bit provides software control for the PLL,
even if PLLCFG is set to ‘0’. The PLL is enabled only
when the HS or EC oscillator frequency is within the
4 MHz to 16 MHz input range.
This enables additional flexibility for controlling the
application’s clock speed in software. The PLLEN
should be enabled in HS or EC Oscillator mode only if
the input frequency is in the range of 4 MHz-16 MHz.
OSC2/CLKO
CEXT
REXT
PIC18FXXXX
OSC1
F
OSC/4
Internal
Clock
VDD
VSS
Recommended values: 3 k  REXT  100 k
20 pF C
EXT  300 pF
CEXT
REXT
PIC18FXXXX
OSC1
Internal
Clock
VDD
VSS
Recommended values: 3 k  REXT  100 k
20 pF C
EXT  300 pF
I/O (OSC2)
RA6
OSC1/CLKI
OSC2/CLKO
F
OSC/4
Clock from
Ext. System
PIC18F87K90
OSC1
OSC2
Open
Clock from
Ext. System
(HS Mode)
PIC18F87K90