Datasheet

PIC18F87K90 FAMILY
DS39957D-page 348  2009-2011 Microchip Technology Inc.
TABLE 21-4: REGISTERS ASSOCIATED WITH I
2
C™ OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 75
PIR1
— ADIF RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF 77
PIE1 — ADIE RC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE 77
IPR1 — ADIP RC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP 77
PIR2
OSCFIF — SSP2IF BLC2IF BCL1IF HLVDIF TMR3IF TMR3GIF 77
PIE2 OSCFIE — SSP2IE BLC2IE BCL1IE HLVDIE TMR3IE TMR3GIE 77
IPR2 OSCFIP — SSP2IP BLC2IP BCL1IP HLVDIP TMR3IP TMR3GIP 77
PIR3 TMR5GIF
LCDIF RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF 77
PIE3 TMR5GIE LCDIE RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE 77
IPR3 TMR5GIP LCDIP RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP 77
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 78
TRISD
TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 78
SSP1BUF MSSP1 Receive Buffer/Transmit Register 76
SSP1ADD MSSP1 Address Register (I
2
C™ Slave mode),
MSSP1 Baud Rate Reload Register (I
2
C Master mode)
76
SSP1MSK
(1)
MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 —
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 76
SSP1CON2
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
76
GCEN ACKSTAT ADMSK5
(2)
ADMSK4
(2)
ADMSK3
(2)
ADMSK2
(2)
ADMSK1
(2)
SEN
SSP1STAT SMP CKE D/A
PSR/WUA BF
76
SSP2BUF MSSP2 Receive Buffer/Transmit Register 82
SSP2ADD MSSP2 Address Register (I
2
C Slave mode),
MSSP2 Baud Rate Reload Register (I
2
C Master mode)
82
SSP2MSK
(1)
MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 —
SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 82
SSP2CON2
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
83
GCEN
ACKSTAT ADMSK5
(2)
ADMSK4
(2)
ADMSK3
(2)
ADMSK2
(2)
ADMSK1
(2)
SEN
SSP2STAT SMP CKE D/A
PSR/WUA BF
82
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I
2
C™ mode.
Note 1: SSPxMSK shares the same address in SFR space as SSPxADD, but is only accessible in certain I
2
C™
Slave operating modes in 7-Bit Masking mode. See Section 21.4.3.4 “7-Bit Address Masking Mode” for
more details.
2: Alternate bit definitions for use in I
2
C Slave mode operations only.