Datasheet
PIC18F87K90 FAMILY
DS39957D-page 26 2009-2011 Microchip Technology Inc.
PORTC is a bidirectional I/O port.
RC0/SOSCO/SCKLI
RC0
SOSCO
SCKLI
36
I/O
O
I
ST
—
ST
Digital I/O.
SOSC oscillator output.
Digital SOSC input.
RC1/SOSCI/ECCP2/
SEG32/P2A
RC1
SOSCI
ECCP2
(1)
SEG32
P2A
35
I/O
I
I/O
O
O
ST
CMOS
ST
Analog
—
Digital I/O.
SOSC oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
SEG32 output for LCD.
Enhanced PWM2 Output A.
RC2/ECCP1/P1A/SEG13
RC2
ECCP1
P1A
SEG13
43
I/O
I/O
O
O
ST
ST
—
Analog
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
Enhanced PWM1 Output A.
SEG13 output for LCD.
RC3/SCK1/SCL1/SEG17
RC3
SCK1
SCL1
SEG17
44
I/O
I/O
I/O
O
ST
ST
ST
Analog
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I
2
C™ mode.
SEG17 output for LCD.
RC4/SDI1/SDA1/SEG16
RC4
SDI1
SDA1
SEG16
45
I/O
I
I/O
O
ST
ST
ST
Analog
Digital I/O.
SPI data in.
I
2
C data I/O.
SEG16 output for LCD.
RC5/SDO1/SEG12
RC5
SDO1
SEG12
46
I/O
O
O
ST
—
Analog
Digital I/O.
SPI data out.
SEG12 output for LCD.
RC6/TX1/CK1/SEG27
RC6
TX1
CK1
SEG27
37
I/O
O
I/O
O
ST
—
ST
Analog
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX1/DT1).
SEG27 output for LCD.
RC7/RX1/DT1/SEG28
RC7
RX1
DT1
SEG28
38
I/O
I
I/O
O
ST
ST
ST
Analog
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX1/CK1).
SEG28 output for LCD.
TABLE 1-4: PIC18F8XK90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
I
2
C™ = I
2
C/SMBus
Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared.
3: Not available on PIC18F65K90 and PIC18F85K90 devices.
4: The CCP6, CCP7, CCP8 and CCP9 pin placement depends on the ECCPMX Configuration bit setting.