Information
Table Of Contents
- TABLE 1: Silicon DEVREV Values
- TABLE 2: Silicon Issue Summary
- Silicon Errata Issues
- 1. Module: Analog-to-Digital Converter (A/D)
- 2. Module: Ports
- 3. Module: High/Low Voltage Detect (HLVD)
- 4. Module: ECCP
- 5. Module: EUSART
- 6. Module: Ipd and Idd
- 7. Module: Ultra Low-Power Sleep
- 8. Module: Resets (BOR)
- 9. Module: RG5 Pin
- 10. Module: Primary Oscillator (XT Mode)
- Data Sheet Clarifications
- 1. Module: Electrical Characteristics
- 2. Module: Voltage Regulator Pins (ENVREG and Vcap/Vddcore)
- 3. Module: DC Characteristics (Injection Current)
- 4. Module: DC Characteristics (Input Low Voltage and Input High Voltage)
- Appendix A: Document Revision History
- Trademarks
- Worldwide Sales

2010-2013 Microchip Technology Inc. DS80000500F-page 9
PIC18F87K90 FAMILY
Data Sheet Clarifications
The following typographic corrections and clarifications
are to be noted for the latest version of the device data
sheet (DS39957D):
1. Module: Electrical Characteristics
Table 31-25 A/D Converter Characteristics has
been corrected. The changes are shown in bold
in the table below:
2. Module: Voltage Regulator Pins
(ENVREG and V
CAP/VDDCORE)
In Section 2.4 “Voltage Regulator Pins
(ENVREG and V
CAP/VDDCORE)”, the
description of the Regulator Disabled mode has
changed. The changes are shown in bold
below:
When the regulator is disabled, the V
CAP/
V
DDCORE pin must only be tied to a 0.1 µF
capacitor. Refer to Section 31.0 “Electrical
Characteristics” for information on V
DD and
V
DDCORE.
Note: Corrections are shown in bold. Where
possible, the original bold text formatting
has been removed for clarity.
TABLE 31-25: A/D CONVERTER CHARACTERISTICS: PIC18F87K90 FAMILY (INDUSTRIAL)
Param.
No.
Sym. Characteristic Min. Typ. Max. Units Conditions
A01 N
R Resolution — — 12 bit VREF 5.0V
A03 EIL Integral Linearity Error — ±1 ±6.0 LSB VREF 5.0V
A04 EDL Differential Linearity Error — ±1 +3.0/-1.0 LSB VREF 5.0V
A06 E
OFF Offset Error — ±1 ±18.0 LSB VREF 5.0V
A07 EGN Gain Error — ±1 ±8.0 LSB VREF 5.0V
A10 — Monotonicity
(1)
————VSS VAIN VREF
A20 VREF Reference Voltage Range
(V
REFH – VREFL)
3—V
DD – VSS V
A21 V
REFH Reference Voltage High VSS + 3.0V — VDD + 0.3V V
A22 V
REFL Reference Voltage Low VSS – 0.3V — VDD – 3.0V V
A25 VAIN Analog Input Voltage VREFL —VREFH V
A30 ZAIN Recommended Impedance
of Analog Voltage Source
——2.5k
A50 I
REF VREF Input Current
(2)
—
—
—
—
5
150
A
A
During VAIN acquisition.
During A/D conversion cycle.
Note 1: The A/D conversion result never decreases with an increase in the input voltage.
2: V
REFH current is from the RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL
current is from the RA2/AN2/V
REF-/CVREF pin or VSS, whichever is selected as the VREFL source.