Datasheet

PIC18F87J90 FAMILY
DS39933D-page 80  2010 Microchip Technology Inc.
RTCVALL RTCC Value Low Register Window based on RTCPTR<1:0> xxxx xxxx 64, 160
ALRMCFG ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0
0000 0000 64, 159
ALRMRPT ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0
0000 0000 64, 160
ALRMVALH Alarm Value High Register Window based on ALRMPTR<1:0>
xxxx xxxx 64, 163
ALRMVALL Alarm Value Low Register Window based on ALRMPTR<1:0>
xxxx xxxx 64, 163
CTMUCONH CTMUEN
— CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 0-00 0000 64, 321
CTMUCONL EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT
0000 0000 64, 322
CTMUICON ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0
0000 0000 64, 323
PADCFG1
— — — — — RTSECSEL1 RTSECSEL0 — ---- -00- 64, 158
TABLE 6-3: PIC18F87J90 FAMILY REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details on
page
Legend:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘ 0 ’. Reset states shown are
for 80-pin devices.
3: Alternate names and definitions for these bits when the MSSP module is operating in I
2
C™ Slave mode. See Section 18.4.3.2 “Address
Masking”
for details.
4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘ 0 ’. See Section 3.4.3 “PLL
Frequency Multiplier”
for details.
5: RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit =
0 ); otherwise, they are disabled and these bits read as ‘ 0 ’.