Datasheet

 2010 Microchip Technology Inc. DS39933D-page 443
PIC18F87J90 FAMILY
Operation
Calibration......................................................... 168
Clock Source .................................................... 166
Digit Carry Rules............................................... 166
General Functionality........................................ 167
Leap Year ......................................................... 167
Register Mapping.............................................. 167
ALRMVAL................................................. 168
RTCVAL.................................................... 167
Safety Window for Register Reads
and Writes................................................. 167
Write Lock......................................................... 167
Register Interface...................................................... 165
Register Maps........................................................... 171
Reset......................................................................... 170
Device............................................................... 170
Power-on Reset (POR)..................................... 170
Sleep Mode............................................................... 170
Value Registers (RTCVAL) ....................................... 160
RTCEN Bit Write ............................................................... 165
S
SCK................................................................................... 211
SDI .................................................................................... 211
SDO .................................................................................. 211
SEC_IDLE Mode................................................................. 50
SEC_RUN Mode................................................................. 46
Serial Clock, SCK ............................................................. 211
Serial Data In (SDI)........................................................... 211
Serial Data Out (SDO) ...................................................... 211
Serial Peripheral Interface. See SPI Mode.
SETF................................................................................. 373
Slave Select (SS
).............................................................. 211
SLEEP .............................................................................. 374
Software Simulator (MPLAB SIM)..................................... 391
Special Event Trigger. See Compare (CCP Module).
Special Features of the CPU ............................................ 325
SPI Mode (MSSP)
Associated Registers ................................................ 219
Bus Mode Compatibility ............................................ 219
Effects of a Reset...................................................... 219
Enabling SPI I/O ....................................................... 215
Master Mode ............................................................. 216
Operation .................................................................. 214
Operation in Power-Managed Modes ....................... 219
Serial Clock............................................................... 211
Serial Data In ............................................................ 211
Serial Data Out ......................................................... 211
Slave Mode ............................................................... 217
Slave Select .............................................................. 211
Slave Select Synchronization ................................... 217
SPI Clock .................................................................. 216
Typical Connection ................................................... 215
SS
..................................................................................... 211
SSPOV.............................................................................. 245
SSPOV Status Flag .......................................................... 245
SSPSTAT Register
R/W
Bit.............................................................. 225, 227
Stack Full/Underflow Resets ............................................... 69
SUBFSR ........................................................................... 385
SUBFWB........................................................................... 374
SUBLW ............................................................................. 375
SUBULNK ......................................................................... 385
SUBWF ............................................................................. 375
SUBWFB........................................................................... 376
SWAPF ............................................................................. 376
T
Table Pointer Operations (table)......................................... 92
Table Reads/Table Writes .................................................. 69
TBLRD.............................................................................. 377
TBLWT ............................................................................. 378
Timer0 .............................................................................. 139
Associated Registers ................................................ 141
Clock Source Select (T0CS Bit) ............................... 140
Operation.................................................................. 140
Overflow Interrupt ..................................................... 141
Prescaler .................................................................. 141
Switching Assignment ...................................... 141
Prescaler Assignment (PSA Bit)............................... 141
Prescaler Select (T0PS2:T0PS0 Bits) ...................... 141
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode............................. 140
Source Edge Select (T0SE Bit) ................................ 140
Timer1 .............................................................................. 143
16-Bit Read/Write Mode ........................................... 145
Associated Registers ................................................ 147
Interrupt .................................................................... 146
Operation.................................................................. 144
Oscillator........................................................... 143, 145
Layout Considerations...................................... 146
Oscillator as Secondary Clock.................................... 37
Overflow Interrupt ..................................................... 143
Resetting, Using the CCP Special
Event Trigger.................................................... 146
TMR1H Register....................................................... 143
TMR1L Register ....................................................... 143
Use as a Clock Source ............................................. 145
Use as a Real-Time Clock ........................................ 146
Timer2 .............................................................................. 149
Associated Registers ................................................ 150
Interrupt .................................................................... 150
Operation.................................................................. 149
Output....................................................................... 150
PR2 Register ............................................................ 179
TMR2 to PR2 Match Interrupt................................... 179
Timer3 .............................................................................. 151
16-Bit Read/Write Mode ........................................... 153
Associated Registers ................................................ 153
Operation.................................................................. 152
Oscillator........................................................... 151, 153
Overflow Interrupt............................................. 151, 153
Special Event Trigger (CCP) .................................... 153
TMR3H Register....................................................... 151
TMR3L Register ....................................................... 151
Timing Diagrams
A/D Conversion ........................................................ 426
Acknowledge Sequence ........................................... 248
Asynchronous Reception.................................. 267, 283
Asynchronous Transmission ............................ 265, 281
Asynchronous Transmission
(Back to Back) .......................................... 265, 281
Automatic Baud Rate Calculation............................. 263
Auto-Wake-up Bit (WUE) During
Normal Operation ............................................. 268
Auto-Wake-up Bit (WUE) During Sleep.................... 268
Baud Rate Generator with Clock Arbitration............. 242
BRG Overflow Sequence ......................................... 263
BRG Reset Due to SDA Arbitration During
Start Condition.................................................. 251
Bus Collision During a Repeated Start
Condition (Case 1)............................................ 252