Datasheet

PIC18F87J90 FAMILY
DS39933D-page 278  2010 Microchip Technology Inc.
20.2 AUSART Baud Rate Generator
(BRG)
The BRG is a dedicated, 8-bit generator that supports
both the Asynchronous and Synchronous modes of the
AUSART.
The SPBRG2 register controls the period of a
free-running timer. In Asynchronous mode, the BRGH
bit (TXSTA<2>) also controls the baud rate. In
Synchronous mode, BRGH is ignored. Table 20-1
shows the formula for computation of the baud rate for
different AUSART modes, which only apply in Master
mode (internally generated clock).
Given the desired baud rate and F
OSC, the nearest
integer value for the SPBRG2 register can be calculated
using the formulas in Table 20-1. From this, the error in
baud rate can be determined. An example calculation is
shown in Example 20-1. Typical baud rates and error
values for the various Asynchronous modes are shown
in Table 20-2. It may be advantageous to use the high
baud rate (BRGH = 1) to reduce the baud rate error, or
achieve a slow baud rate for a fast oscillator frequency.
Writing a new value to the SPBRG2 register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before outputting
the new baud rate.
20.2.1 OPERATION IN POWER-MANAGED
MODES
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRG2 register.
20.2.2 SAMPLING
The data on the RX2 pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RX2 pin.
TABLE 20-1: BAUD RATE FORMULAS
EXAMPLE 20-1: CALCULATING BAUD RATE ERROR
TABLE 20-2: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Configuration Bits
BRG/AUSART Mode Baud Rate Formula
SYNC BRGH
00 Asynchronous F
OSC/[64 (n + 1)]
01 Asynchronous F
OSC/[16 (n + 1)]
1x Synchronous FOSC/[4 (n + 1)]
Legend: x = Don’t care, n = Value of SPBRG2 register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values on
Page
TXSTA2
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 64
RCSTA2 SPEN
RX9 SREN CREN ADDEN FERR OERR RX9D 64
SPBRG2 AUSART Baud Rate Generator Register 64
Legend: Shaded cells are not used by the BRG.
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, BRGH = 0:
Desired Baud Rate = F
OSC/(64 ([SPBRG2] + 1))
Solving for SPBRG2:
X = ((F
OSC/Desired Baud Rate)/64) – 1
= ((16000000/9600)/64) – 1
= [25.042] = 25
Calculated Baud Rate = 16000000/(64 (25 + 1))
= 9615
Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
= (9615 – 9600)/9600 = 0.16%