Datasheet

PIC18F87J11 FAMILY
DS39778E-page 460  2007-2012 Microchip Technology Inc.
Timing Diagrams
A/D Conversion ........................................................ 439
Asynchronous Reception ......................................... 298
Asynchronous Transmission .................................... 296
Asynchronous Transmission (Back to Back) ........... 296
Automatic Baud Rate Calculation ............................ 294
Auto-Wake-up Bit (WUE) During
Normal Operation .............................................301
Auto-Wake-up Bit (WUE) During Sleep ...................301
Baud Rate Generator with Clock Arbitration ............271
BRG Overflow Sequence ......................................... 294
BRG Reset Due to SDAx Arbitration During
Start Condition .................................................280
Bus Collision During a Repeated Start
Condition (Case 1) ........................................... 281
Bus Collision During a Repeated Start
Condition (Case 2) ........................................... 281
Bus Collision During a Start Condition
(SCLx = 0) ........................................................ 280
Bus Collision During a Stop Condition (Case 1) ......282
Bus Collision During a Stop Condition (Case 2) ......282
Bus Collision During Start Condition (SDAx Only) ... 279
Bus Collision for Transmit and Acknowledge ........... 278
Capture/Compare/PWM (Including
ECCP Modules) ...............................................429
CLKO and I/O .......................................................... 420
Clock Synchronization .............................................264
Clock/Instruction Cycle ..............................................74
EUSARTx Synchronous Receive (Master/Slave) ....438
EUSARTx Synchronous Transmission
(Master/Slave) ..................................................438
Example SPI Master Mode (CKE = 0) ..................... 430
Example SPI Master Mode (CKE = 1) ..................... 431
Example SPI Slave Mode (CKE = 0) ....................... 432
Example SPI Slave Mode (CKE = 1) ....................... 433
External Clock .......................................................... 418
External Memory Bus for Sleep (Extended
Microcontroller Mode) .............................. 112, 114
External Memory Bus for TBLRD (Extended
Microcontroller Mode) .............................. 112, 114
Fail-Safe Clock Monitor ............................................344
First Start Bit Timing ................................................272
Full-Bridge PWM Output .......................................... 228
Half-Bridge PWM Output .........................................227
I
2
C Acknowledge Sequence ....................................277
I
2
C Bus Data ............................................................434
I
2
C Bus Start/Stop Bits .............................................434
I
2
C Master Mode (7 or 10-Bit Transmission) ........... 275
I
2
C Master Mode (7-Bit Reception) ..........................276
I
2
C Slave Mode (10-Bit Reception, SEN = 0,
ADMSK = 01001) ............................................. 260
I
2
C Slave Mode (10-Bit Reception, SEN = 0) .......... 261
I
2
C Slave Mode (10-Bit Reception, SEN = 1) .......... 266
I
2
C Slave Mode (10-Bit Transmission) ..................... 262
I
2
C Slave Mode (7-bit Reception, SEN = 0,
ADMSK = 01011) ............................................. 258
I
2
C Slave Mode (7-Bit Reception, SEN = 0) ............ 257
I
2
C Slave Mode (7-Bit Reception, SEN = 1) ............ 265
I
2
C Slave Mode (7-Bit Transmission) ....................... 259
I
2
C Slave Mode General Call Address Sequence
(7 or 10-Bit Addressing Mode) ......................... 267
I
2
C Stop Condition Receive or Transmit Mode ........ 277
MSSPx I
2
C Bus Data ...............................................436
MSSPx I
2
C Bus Start/Stop Bits ................................436
Parallel Master Port Read ........................................427
Parallel Master Port Write ........................................ 428
Parallel Slave Port ................................................... 426
Parallel Slave Port Read .................................. 176, 179
Parallel Slave Port Write .................................. 176, 179
Program Memory Fetch (8-Bit) ................................ 421
Program Memory Read ........................................... 422
Program Memory Write ............................................ 423
PWM Auto-Shutdown (P1RSEN = 0,
Auto-Restart Disabled) .................................... 233
PWM Auto-Shutdown (P1RSEN = 1,
Auto-Restart Enabled) ..................................... 233
PWM Direction Change ........................................... 230
PWM Direction Change at Near
100% Duty Cycle ............................................. 230
PWM Output ............................................................ 216
Read and Write, 8-Bit Data, Demultiplexed
Address ........................................................... 183
Read, 16-Bit Data, Demultiplexed Address ............. 186
Read, 16-Bit Multiplexed Data, Fully Multiplexed
16-Bit Address ................................................. 188
Read, 16-Bit Multiplexed Data, Partially
Multiplexed Address ........................................ 187
Read, 8-Bit Data, Fully Multiplexed
16-Bit Address ................................................. 185
Read, 8-Bit Data, Partially Multiplexed Address ...... 183
Read, 8-Bit Data, Partially Multiplexed
Address, Enable Strobe ................................... 185
Read, 8-Bit Data, Wait States Enabled,
Partially Multiplexed Address .......................... 184
Repeated Start Condition ........................................ 273
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT) ..... 424
Send Break Character Sequence ............................ 302
Slave Synchronization ............................................. 244
Slow Rise (MCLR
Tied to VDD,
V
DD Rise > TPWRT) ............................................ 59
SPI Mode (Master Mode) ......................................... 243
SPI Mode (Slave Mode, CKE = 0) ........................... 245
SPI Mode (Slave Mode, CKE = 1) ........................... 245
Synchronous Reception (Master Mode, SREN) ...... 305
Synchronous Transmission ..................................... 303
Synchronous Transmission (Through TXEN) .......... 304
Time-out Sequence on Power-up (MCLR
Not
Tied to V
DD), Case 1 ......................................... 59
Time-out Sequence on Power-up (MCLR
Not
Tied to V
DD), Case 2 ......................................... 59
Time-out Sequence on Power-up (MCLR
Tied
to V
DD, VDD Rise < TPWRT) ............................... 58
Timer0 and Timer1 External Clock .......................... 425
Transition for Entry to Idle Mode ................................ 52
Transition for Entry to SEC_RUN Mode .................... 49
Transition for Entry to Sleep Mode ............................ 51
Transition for Two-Speed Start-up
(INTRC to HSPLL) ........................................... 342
Transition for Wake from Idle to Run Mode ............... 52
Transition for Wake from Sleep (HSPLL) .................. 51
Transition from RC_RUN Mode to
PRI_RUN Mode ................................................. 50
Transition from SEC_RUN Mode to
PRI_RUN Mode (HSPLL) .................................. 49
Transition to RC_RUN Mode ..................................... 50
Write, 16-Bit Multiplexed Data, Fully Multiplexed
16-Bit Address ................................................. 188
Write, 16-Bit Multiplexed Data, Partially
Multiplexed Address ........................................ 187