Datasheet
PIC18F87J11 FAMILY
DS39778E-page 440 2007-2012 Microchip Technology Inc.
TABLE 28-31: A/D CONVERSION REQUIREMENTS
Param
No.
Symbol Characteristic Min Max Units Conditions
130 T
AD A/D Clock Period 0.7 25.0
(1)
sTOSC based, VREF 3.0V
—1s A/D RC mode
131 T
CNV Conversion Time
(not including acquisition time) (Note 2)
11 12 TAD
132 TACQ Acquisition Time (Note 3) 1.4 — s-40C to +85C
135 T
SWC Switching Time from Convert Sample — (Note 4)
136 TDIS Discharge Time 0.2 — s
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: The ADRES registers may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
DD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50.
4: On the following cycle of the device clock.