Datasheet

PIC18F87J11 FAMILY
DS39778E-page 298  2007-2012 Microchip Technology Inc.
FIGURE 21-6: EUSARTx RECEIVE BLOCK DIAGRAM
FIGURE 21-7: ASYNCHRONOUS RECEPTION
x64 Baud Rate CLK
Baud Rate Generator
RXx
Pin Buffer
and Control
SPEN
Data
Recovery
CREN
OERR
FERR
RSR Register
MSb
LSb
RX9D RCREGx Register
FIFO
Interrupt
RCxIF
RCxIE
Data Bus
8
 64
 16
or
Stop
Start
(8) 7 1 0
RX9

SPBRGx
SPBRGHx
BRG16
or
 4
Start
bit
bit 7/8bit 1bit 0 bit 7/8 bit 0
Stop
bit
Start
bit
Start
bit
bit 7/8
Stop
bit
RXx (pin)
Rcv Buffer Reg
Rcv Shift Reg
Read Rcv
Buffer Reg
RCREGx
RCxIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREGx
Word 2
RCREGx
Stop
bit
Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word,
causing the OERR (Overrun Error) bit to be set.