Datasheet

 2007-2012 Microchip Technology Inc. DS39778E-page 283
PIC18F87J11 FAMILY
TABLE 20-4: REGISTERS ASSOCIATED WITH I
2
C™ OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61
PIR1
PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64
PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64
IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64
PIR2
OSCFIF CM2IF CM1IF —BCL1IFLVDIF TMR3IF CCP2IF 64
PIE2 OSCFIE CM2IE CM1IE —BCL1IELVDIE TMR3IE CCP2IE 64
IPR2 OSCFIP CM2IP CM1IP —BCL1IPLVDIP TMR3IP CCP2IP 64
PIR3 SSP2IF BCL2IF
RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 64
PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 64
IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 64
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 64
TRISD
TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 64
SSP1BUF MSSP1 Receive Buffer/Transmit Register 62
SSP1ADD MSSP1 Address Register (I
2
C™ Slave mode),
MSSP1 Baud Rate Reload Register (I
2
C Master mode)
62
SSP1MSK
(1)
MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 62
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 62
SSP1CON2
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 62
GCEN ACKSTAT ADMSK5
(2)
ADMSK4
(2)
ADMSK3
(2)
ADMSK2
(2)
ADMSK1
(2)
SEN
SSP1STAT SMP CKE D/A
PSR/WUA BF 62
SSP2BUF MSSP2 Receive Buffer/Transmit Register 65
SSP2ADD MSSP2 Address Register (I
2
C Slave mode),
MSSP2 Baud Rate Reload Register (I
2
C Master mode)
65
SSP2MSK
(1)
MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 65
SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 65
SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 65
GCEN
ACKSTAT ADMSK5
(2)
ADMSK4
(2)
ADMSK3
(2)
ADMSK2
(2)
ADMSK1
(2)
SEN
SSP2STAT SMP CKE D/A
PSR/WUA BF 65
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I
2
C mode.
Note 1: SSPxMSK shares the same address in SFR space as SSPxADD, but is only accessible in certain I
2
C™
Slave operating modes in 7-Bit Masking mode. See Section 20.4.3.4 “7-Bit Address Masking Mode” for
more details.
2: Alternate bit definitions for use in I
2
C Slave mode operations only.