Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 64 (10x10) 8-Bit 48 MHz I/O number 52

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DS39778E-page 252  2007-2012 Microchip Technology Inc.

C™ SLAVE MODE)

C™ SLAVE ADDRESS MASK REGISTER

(7-BIT MASKING MODE)

(1)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GCEN ACKSTAT ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1 SEN

(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GCEN: General Call Enable bit

1 = Enables interrupt when a general call address (0000h) is received in the SSPxSR

0 = General call address is disabled

bit 6 ACKSTAT: Acknowledge Status bit

Unused in Slave mode.

bit 5-2 ADMSK5:ADMSK2: Slave Address Mask Select bits (5-Bit Address Masking mode)

1 = Masking of the corresponding bits of SSPxADD is enabled

0 = Masking of the corresponding bits of SSPxADD is disabled

bit 1 ADMSK1: Slave Address Least Significant bit(s) Mask Select bit

In 7-Bit Addressing mode:

1 = Masking of SSPxADD<1> only is enabled

0 = Masking of SSPxADD<1> only is disabled

In 10-Bit Addressing mode:

1 = Masking of SSPxADD<1:0> is enabled

0 = Masking of SSPxADD<1:0> is disabled

bit 0 SEN: Stretch Enable bit

(1)

1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)

0 = Clock stretching is disabled

Note 1: If the I

C module is active, this bit may not be set (no spooling) and the SSPxBUF may not be written (or

writes to the SSPxBUF are disabled).

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0

(2)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 MSK<7:0>: Slave Address Mask Select bit

(2)

1 = Masking of the corresponding bit of SSPxADD is enabled

0 = Masking of the corresponding bit of SSPxADD is disabled

Note 1: This register shares the same SFR address as SSPxADD and is only addressable in select MSSPx

operating modes. See Section 20.4.3.4 “7-Bit Address Masking Mode” for more details.

2: MSK0 is not used as a mask bit in 7-bit addressing.