Datasheet

PIC18F87J10 FAMILY
DS39663F-page 404 © 2009 Microchip Technology Inc.
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C Slave Mode (10-Bit Reception, SEN = 0,
ADMSK = 01001) ............................................. 215
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C Slave Mode (10-Bit Reception, SEN = 0) .......... 216
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C Slave Mode (10-Bit Reception, SEN = 1) .......... 221
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C Slave Mode (10-Bit Transmission) ..................... 217
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C Slave Mode (7-Bit Reception, SEN = 0,
ADMSK = 01011) ............................................. 213
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C Slave Mode (7-Bit Reception, SEN = 0) ............ 212
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C Slave Mode (7-Bit Reception, SEN = 1) ............ 220
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C Slave Mode (7-Bit Transmission) ....................... 214
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C Slave Mode General Call Address Sequence
(7 or 10-Bit Addressing Mode) ......................... 222
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C Stop Condition Receive or Transmit Mode ........ 232
Master SSP I
2
C Bus Data ........................................ 379
Master SSP I
2
C Bus Start/Stop Bits ........................ 379
Parallel Slave Port (PSP) Read ............................... 150
Parallel Slave Port (PSP) Write ...............................149
Program Memory Read ............................................ 368
Program Memory Write ............................................ 369
PWM Auto-Shutdown (P1RSEN = 0,
Auto-Restart Disabled) ..................................... 190
PWM Auto-Shutdown (P1RSEN = 1,
Auto-Restart Enabled) ..................................... 190
PWM Direction Change ........................................... 187
PWM Direction Change at Near
100% Duty Cycle ............................................. 187
PWM Output ............................................................ 174
Repeated Start Condition ......................................... 228
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT) ..... 370
Send Break Character Sequence ............................ 254
Slave Synchronization ............................................. 199
Slow Rise Time (MCLR
Tied to VDD,
V
DD Rise > TPWRT) ............................................ 51
SPI Mode (Master Mode) ......................................... 198
SPI Mode (Slave Mode, CKE = 0) ........................... 200
SPI Mode (Slave Mode, CKE = 1) ........................... 200
Synchronous Reception (Master Mode, SREN) ...... 257
Synchronous Transmission ...................................... 255
Synchronous Transmission (Through TXEN) .......... 256
Time-out Sequence on Power-up
(MCLR
Not Tied to VDD), Case 1 ....................... 50
Time-out Sequence on Power-up
(MCLR
Not Tied to VDD), Case 2 ....................... 51
Time-out Sequence on Power-up
(MCLR
Tied to VDD, VDD Rise < TPWRT) ...........50
Timer0 and Timer1 External Clock .......................... 371
Transition for Entry to Idle Mode ................................ 44
Transition for Entry to SEC_RUN Mode .................... 41
Transition for Entry to Sleep Mode ............................ 43
Transition for Two-Speed Start-up
(INTRC to HSPLL) ........................................... 289
Transition for Wake From Idle to Run Mode .............. 44
Transition for Wake From Sleep (HSPLL) ................. 43
Transition From RC_RUN Mode to
PRI_RUN Mode ................................................. 42
Transition from SEC_RUN Mode to
PRI_RUN Mode (HSPLL) .................................. 41
Transition to RC_RUN Mode ..................................... 42
Timing Diagrams and Specifications
AC Characteristics
Internal RC Accuracy .......................................365
Capture/Compare/PWM Requirements
(Including ECCP Modules) .............................. 372
CLKO and I/O Requirements ........................... 366, 368
EUSART Synchronous Receive
Requirements .................................................. 381
EUSART Synchronous Transmission
Requirements .................................................. 381
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 373
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 374
Example SPI Mode Requirements
(Slave Mode, CKE = 0) .................................... 375
Example SPI Slave Mode Requirements
(CKE = 1) ......................................................... 376
External Clock Requirements .................................. 364
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C Bus Data Requirements (Slave Mode) .............. 378
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C Bus Start/Stop Bits Requirements
(Slave Mode) ................................................... 377
Master SSP I
2
C Bus Data Requirements ................ 380
Master SSP I
2
C Bus Start/Stop Bits
Requirements .................................................. 379
Parallel Slave Port Requirements ............................ 372
PLL Clock ................................................................ 365
Program Memory Write Requirements .................... 369
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 370
Timer0 and Timer1 External Clock
Requirements .................................................. 371
Top-of-Stack Access .......................................................... 63
TRISE Register
PSPMODE Bit .......................................................... 148
TSTFSZ ........................................................................... 333
Two-Speed Start-up ................................................. 281, 289
Two-Word Instructions
Example Cases .......................................................... 67
TXSTAx Register
BRGH Bit ................................................................. 243
U
Unused I/Os ....................................................................... 30
V
VDDCORE/VCAP Pin .......................................................... 288
Voltage Reference Specifications .................................... 361
Voltage Regulator (On-Chip) ........................................... 288
W
Watchdog Timer (WDT) ........................................... 281, 287
Associated Registers ............................................... 287
Control Register ....................................................... 287
During Oscillator Failure .......................................... 290
Programming Considerations .................................. 287
WCOL ...................................................... 227, 228, 229, 232
WCOL Status Flag ................................... 227, 228, 229, 232
WWW Address ................................................................ 405
WWW, On-Line Support ...................................................... 4
X
XORLW ............................................................................ 333
XORWF ........................................................................... 334