Datasheet

PIC18F87J10 FAMILY
DS39663F-page 288 © 2009 Microchip Technology Inc.
24.3 On-Chip Voltage Regulator
All of the PIC18F87J10 family devices power their core
digital logic at a nominal 2.5V. For designs that are
required to operate at a higher typical voltage, such as
3.3V, all devices in the PIC18F87J10 family incorporate
an on-chip regulator that allows the device to run its
core logic from V
DD.
The regulator is controlled by the ENVREG pin. Tying
VDD to the pin enables the regulator, which in turn, pro-
vides power to the core from the other V
DD pins. When
the regulator is enabled, a low-ESR filter capacitor
must be connected to the VDDCORE/VCAP pin
(Figure 24-2). This helps to maintain the stability of the
regulator. The recommended value for the filter capac-
itor is provided in Section 27.3 “DC Characteristics:
PIC18F87J10 Family (Industrial)”.
If ENVREG is tied to V
SS, the regulator is disabled. In
this case, separate power for the core logic at a nomi-
nal 2.5V must be supplied to the device on the
V
DDCORE/VCAP pin to run the I/O pins at higher voltage
levels, typically 3.3V. Alternatively, the V
DDCORE/VCAP
and VDD pins can be tied together to operate at a lower
nominal voltage. Refer to Figure 24-2 for possible
configurations.
24.3.1 ON-CHIP REGULATOR AND BOR
When the on-chip regulator is enabled, PIC18F87J10
family devices also have a simple brown-out capability.
If the voltage supplied to the regulator is inadequate to
maintain a regulated level, the regulator Reset circuitry
will generate a BOR Reset. This event is captured by
the BOR
flag bit (RCON<0>).
The operation of the BOR is described in more detail in
Section 5.4 “Brown-out Reset (BOR)” and
Section 5.4.1 “Detecting BOR”. The brown-out voltage
levels are specific in Section 27.1 “DC Characteristics:
Supply Voltage, PIC18F87J10 Family (Industrial)”.
24.3.2 POWER-UP REQUIREMENTS
The on-chip regulator is designed to meet the power-up
requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
be adhered to. While powering up, V
DDCORE must
never exceed V
DD by 0.3 volts.
FIGURE 24-2: CONNECTIONS FOR THE
ON-CHIP REGULATOR
VDD
ENVREG
V
DDCORE/VCAP
VSS
PIC18FXXJ10/XXJ15
3.3V
(1)
2.5V
(1)
VDD
ENVREG
V
DDCORE/VCAP
VSS
PIC18FXXJ10/XXJ15
CF
3.3V
Regulator Enabled (ENVREG tied to VDD):
Regulator Disabled (ENVREG tied to ground):
VDD
ENVREG
V
DDCORE/VCAP
VSS
PIC18FXXJ10/XXJ15
2.5V
(1)
Regulator Disabled (VDD tied to VDDCORE):
Note 1: These are typical operating voltages. Refer
to Section 27.1 “DC Characteristics:
Supply Voltage” for the full operating
ranges of V
DD and VDDCORE.