Datasheet

PIC18F87J10 FAMILY
DS39663F-page 256 © 2009 Microchip Technology Inc.
FIGURE 20-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
TABLE 20-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53
PIR1
PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 55
PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 55
IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 55
PIR3
SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 55
PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 55
IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 55
RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 55
TXREGx EUSARTx Transmit Register 55
TXSTAx CSRC TX9 TXEN SYNC
SENDB BRGH TRMT TX9D 55
BAUDCONx
ABDOVF RCIDL —SCKPBRG16— WUE ABDEN 56
SPBRGHx EUSARTx Baud Rate Generator Register High Byte 56
SPBRGx EUSARTx Baud Rate Generator Register Low Byte 56
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
RC7/RX1/DT1 pin
RC6/TX1/CK1 pin
Write to
TXREG1 reg
TX1IF bit
TRMT bit
bit 0
bit 1
bit 2
bit 6 bit 7
TXEN bit
Note: This example is equally applicable to EUSART2 (RG1/TX2/CK2 and RG2/RX2/DT2).